SOURCES: glibc-sparc-softfp-gcc.patch (NEW) - recent gcc versions ...

[qboosh]

Author: qboosh                       Date: Sat Dec 30 20:26:06 2006 GMT
Module: SOURCES                       Tag: HEAD
---- Log message:
- recent gcc versions allow up to 30 asm parameters and don't like to clobber register reserved for variable

---- Files affected:
SOURCES:
   glibc-sparc-softfp-gcc.patch (NONE -> 1.1)  (NEW)

---- Diffs:

================================================================
Index: SOURCES/glibc-sparc-softfp-gcc.patch
diff -u /dev/null SOURCES/glibc-sparc-softfp-gcc.patch:1.1
--- /dev/null	Sat Dec 30 21:26:06 2006
+++ SOURCES/glibc-sparc-softfp-gcc.patch	Sat Dec 30 21:26:00 2006
@@ -0,0 +1,69 @@
+--- glibc-2.5/sysdeps/sparc/sparc32/soft-fp/sfp-machine.h.orig	2006-01-14 12:09:02.000000000 +0000
++++ glibc-2.5/sysdeps/sparc/sparc32/soft-fp/sfp-machine.h	2006-12-30 20:17:12.000000000 +0000
+@@ -105,16 +105,15 @@
+ 
+ #define __FP_FRAC_ADD_4(r3,r2,r1,r0,x3,x2,x1,x0,y3,y2,y1,y0)		\
+   do {									\
+-    /* We need to fool gcc,  as we need to pass more than 10		\
+-       input/outputs.  */						\
+-    register USItype _t1 __asm__ ("g1"), _t2 __asm__ ("g2");		\
+     __asm__ __volatile__ ("\
+-	    addcc %r8,%9,%1\n\
+-	    addxcc %r6,%7,%0\n\
+-	    addxcc %r4,%5,%%g2\n\
+-	    addx %r2,%3,%%g1"						\
++	    addcc %r10,%11,%1\n\
++	    addxcc %r7,%9,%0\n\
++	    addxcc %r6,%7,%3\n\
++	    addx %r4,%5,%2"						\
+ 	   : "=&r" ((USItype)(r1)),					\
+-	     "=&r" ((USItype)(r0))					\
++	     "=&r" ((USItype)(r0)),					\
++	     "=&r" ((USItype)(r3)),					\
++	     "=&r" ((USItype)(r2))					\
+ 	   : "%rJ" ((USItype)(x3)),					\
+ 	     "rI" ((USItype)(y3)),					\
+ 	     "%rJ" ((USItype)(x2)),					\
+@@ -123,23 +122,20 @@
+ 	     "rI" ((USItype)(y1)),					\
+ 	     "%rJ" ((USItype)(x0)),					\
+ 	     "rI" ((USItype)(y0))					\
+-	   : "cc", "g1", "g2");						\
+-    __asm__ __volatile__ ("" : "=r" (_t1), "=r" (_t2));			\
+-    r3 = _t1; r2 = _t2;							\
++	   : "cc");							\
+   } while (0)
+ 
+ #define __FP_FRAC_SUB_4(r3,r2,r1,r0,x3,x2,x1,x0,y3,y2,y1,y0)		\
+   do {									\
+-    /* We need to fool gcc,  as we need to pass more than 10		\
+-       input/outputs.  */						\
+-    register USItype _t1 __asm__ ("g1"), _t2 __asm__ ("g2");		\
+     __asm__ __volatile__ ("\
+-	    subcc %r8,%9,%1\n\
+-	    subxcc %r6,%7,%0\n\
+-	    subxcc %r4,%5,%%g2\n\
+-	    subx %r2,%3,%%g1"						\
++	    subcc %r10,%11,%1\n\
++	    subxcc %r8,%9,%0\n\
++	    subxcc %r6,%7,%3\n\
++	    subx %r4,%5,%2"						\
+ 	   : "=&r" ((USItype)(r1)),					\
+-	     "=&r" ((USItype)(r0))					\
++	     "=&r" ((USItype)(r0)),					\
++	     "=&r" ((USItype)(r3)),					\
++	     "=&r" ((USItype)(r2))					\
+ 	   : "%rJ" ((USItype)(x3)),					\
+ 	     "rI" ((USItype)(y3)),					\
+ 	     "%rJ" ((USItype)(x2)),					\
+@@ -148,9 +144,7 @@
+ 	     "rI" ((USItype)(y1)),					\
+ 	     "%rJ" ((USItype)(x0)),					\
+ 	     "rI" ((USItype)(y0))					\
+-	   : "cc", "g1", "g2");						\
+-    __asm__ __volatile__ ("" : "=r" (_t1), "=r" (_t2));			\
+-    r3 = _t1; r2 = _t2;							\
++	   : "cc");							\
+   } while (0)
+ 
+ #define __FP_FRAC_DEC_3(x2,x1,x0,y2,y1,y0) __FP_FRAC_SUB_3(x2,x1,x0,x2,x1,x0,y2,y1,y0)
================================================================