SOURCES: linux-tg3-3.81c.patch (NEW) - from Broadcom http://www.br...
marcus
marcus at pld-linux.org
Fri Feb 8 10:28:36 CET 2008
Author: marcus Date: Fri Feb 8 09:28:36 2008 GMT
Module: SOURCES Tag: HEAD
---- Log message:
- from Broadcom http://www.broadcom.com/support/ethernet_nic/driver-sla.php?driver=570x-Linux zip archive
---- Files affected:
SOURCES:
linux-tg3-3.81c.patch (NONE -> 1.1) (NEW)
---- Diffs:
================================================================
Index: SOURCES/linux-tg3-3.81c.patch
diff -u /dev/null SOURCES/linux-tg3-3.81c.patch:1.1
--- /dev/null Fri Feb 8 10:28:36 2008
+++ SOURCES/linux-tg3-3.81c.patch Fri Feb 8 10:28:30 2008
@@ -0,0 +1,6918 @@
+diff -uNr linux-2.6.16.old/drivers/net/tg3.c linux-2.6.16/drivers/net/tg3.c
+--- linux-2.6.16.old/drivers/net/tg3.c 2008-02-08 09:52:27.000000000 +0100
++++ linux-2.6.16/drivers/net/tg3.c 2007-09-19 00:38:18.000000000 +0200
+@@ -4,7 +4,7 @@
+ * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem at redhat.com)
+ * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik at pobox.com)
+ * Copyright (C) 2004 Sun Microsystems Inc.
+- * Copyright (C) 2005 Broadcom Corporation.
++ * Copyright (C) 2005-2007 Broadcom Corporation.
+ *
+ * Firmware is:
+ * Derived from proprietary unpublished source code,
+@@ -15,10 +15,22 @@
+ * notice is accompanying it.
+ */
+
++#include <linux/version.h>
++
++#if (LINUX_VERSION_CODE < 0x020612)
+ #include <linux/config.h>
++#endif
+
++#if (LINUX_VERSION_CODE < 0x020500)
++#if defined(CONFIG_MODVERSIONS) && defined(MODULE) && ! defined(MODVERSIONS)
++#define MODVERSIONS
++#include <linux/modversions.h>
++#endif
++#endif
+ #include <linux/module.h>
++#if (LINUX_VERSION_CODE >= 0x20600)
+ #include <linux/moduleparam.h>
++#endif
+ #include <linux/kernel.h>
+ #include <linux/types.h>
+ #include <linux/compiler.h>
+@@ -36,21 +48,26 @@
+ #include <linux/if_vlan.h>
+ #include <linux/ip.h>
+ #include <linux/tcp.h>
++#if (LINUX_VERSION_CODE >= 0x20600)
+ #include <linux/workqueue.h>
++#endif
+ #include <linux/prefetch.h>
++#if (LINUX_VERSION_CODE >= 0x020600)
+ #include <linux/dma-mapping.h>
++#endif
++#include <linux/bitops.h>
+
+ #include <net/checksum.h>
++#include <net/ip.h>
+
+ #include <asm/system.h>
+ #include <asm/io.h>
+ #include <asm/byteorder.h>
+ #include <asm/uaccess.h>
+
+-#ifdef CONFIG_SPARC64
++#ifdef CONFIG_SPARC
+ #include <asm/idprom.h>
+-#include <asm/oplib.h>
+-#include <asm/pbm.h>
++#include <asm/prom.h>
+ #endif
+
+ #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
+@@ -69,8 +86,8 @@
+
+ #define DRV_MODULE_NAME "tg3"
+ #define PFX DRV_MODULE_NAME ": "
+-#define DRV_MODULE_VERSION "3.49"
+-#define DRV_MODULE_RELDATE "Feb 2, 2006"
++#define DRV_MODULE_VERSION "3.81c"
++#define DRV_MODULE_RELDATE "September 18, 2007"
+
+ #define TG3_DEF_MAC_MODE 0
+ #define TG3_DEF_RX_MODE 0
+@@ -124,16 +141,13 @@
+ TG3_RX_RCB_RING_SIZE(tp))
+ #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
+ TG3_TX_RING_SIZE)
+-#define TX_BUFFS_AVAIL(TP) \
+- ((TP)->tx_pending - \
+- (((TP)->tx_prod - (TP)->tx_cons) & (TG3_TX_RING_SIZE - 1)))
+ #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
+
+ #define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
+ #define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
+
+ /* minimum number of free TX descriptors required to wake up TX process */
+-#define TG3_TX_WAKEUP_THRESH (TG3_TX_RING_SIZE / 4)
++#define TG3_TX_WAKEUP_THRESH(tp) ((tp)->tx_pending / 4)
+
+ /* number of ETHTOOL_GSTATS u64's */
+ #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
+@@ -149,108 +163,78 @@
+ MODULE_VERSION(DRV_MODULE_VERSION);
+
+ static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
++#if (LINUX_VERSION_CODE >= 0x20600)
+ module_param(tg3_debug, int, 0);
+ MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
++#endif
+
+ static struct pci_device_id tg3_pci_tbl[] = {
+- { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700,
+- PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+- { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701,
+- PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+- { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702,
+- PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+- { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703,
+- PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+- { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704,
+- PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+- { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE,
+- PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+- { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705,
+- PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+- { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2,
+- PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+- { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M,
+- PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+- { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2,
+- PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+- { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X,
+- PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+- { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X,
+- PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+- { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S,
+- PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+- { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3,
+- PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+- { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3,
+- PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+- { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782,
+- PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+- { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788,
+- PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+- { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789,
+- PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+- { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901,
+- PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+- { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2,
+- PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+- { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2,
+- PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+- { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F,
+- PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+- { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720,
+- PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+- { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721,
+- PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+- { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750,
+- PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+- { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751,
+- PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+- { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M,
+- PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+- { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M,
+- PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+- { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F,
+- PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+- { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752,
+- PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+- { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M,
+- PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+- { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753,
+- PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+- { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M,
+- PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+- { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F,
+- PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+- { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714,
+- PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+- { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715,
+- PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+- { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780,
+- PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+- { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S,
+- PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+- { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781,
+- PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+- { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX,
+- PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+- { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX,
+- PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+- { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000,
+- PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+- { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001,
+- PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+- { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003,
+- PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+- { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100,
+- PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+- { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3,
+- PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+- { 0, }
++ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
++ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
++ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
++ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
++ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
++ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
++ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
++ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
++ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
++ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
++ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
++ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
++ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
++ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
++ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
++ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
++ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
++ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
++ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
++ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
++ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
++ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
++ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
++ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
++ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
++ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
++ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
++ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
++ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
++ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
++ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
++ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
++ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
++ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
++ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
++ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
++ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
++ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
++ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
++ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
++ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
++ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
++ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
++ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
++ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
++ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
++ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
++ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
++ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
++ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
++ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
++ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
++ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
++ {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
++ {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
++ {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
++ {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
++ {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
++ {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
++ {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
++ {}
+ };
+
+ MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
+
+-static struct {
++static const struct {
+ const char string[ETH_GSTRING_LEN];
+ } ethtool_stats_keys[TG3_NUM_STATS] = {
+ { "rx_octets" },
+@@ -331,7 +315,7 @@
+ { "nic_tx_threshold_hit" }
+ };
+
+-static struct {
++static const struct {
+ const char string[ETH_GSTRING_LEN];
+ } ethtool_test_keys[TG3_NUM_TEST] = {
+ { "nvram test (online) " },
+@@ -349,7 +333,7 @@
+
+ static u32 tg3_read32(struct tg3 *tp, u32 off)
+ {
+- return (readl(tp->regs + off));
++ return (readl(tp->regs + off));
+ }
+
+ static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
+@@ -465,6 +449,16 @@
+ readl(mbox);
+ }
+
++static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
++{
++ return (readl(tp->regs + off + GRCMBOX_BASE));
++}
++
++static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
++{
++ writel(val, tp->regs + off + GRCMBOX_BASE);
++}
++
+ #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
+ #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
+ #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
+@@ -480,34 +474,51 @@
+ {
+ unsigned long flags;
+
++ if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
++ (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
++ return;
++
+ spin_lock_irqsave(&tp->indirect_lock, flags);
+- pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
+- pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
++ if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
++ pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
++ pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
+
+- /* Always leave this as zero. */
+- pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
+- spin_unlock_irqrestore(&tp->indirect_lock, flags);
+-}
++ /* Always leave this as zero. */
++ pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
++ } else {
++ tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
++ tw32_f(TG3PCI_MEM_WIN_DATA, val);
+
+-static void tg3_write_mem_fast(struct tg3 *tp, u32 off, u32 val)
+-{
+- /* If no workaround is needed, write to mem space directly */
+- if (tp->write32 != tg3_write_indirect_reg32)
+- tw32(NIC_SRAM_WIN_BASE + off, val);
+- else
+- tg3_write_mem(tp, off, val);
++ /* Always leave this as zero. */
++ tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
++ }
++ spin_unlock_irqrestore(&tp->indirect_lock, flags);
+ }
+
+ static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
+ {
+ unsigned long flags;
+
++ if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
++ (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
++ *val = 0;
++ return;
++ }
++
+ spin_lock_irqsave(&tp->indirect_lock, flags);
+- pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
+- pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
++ if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
++ pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
++ pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
+
+- /* Always leave this as zero. */
+- pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
++ /* Always leave this as zero. */
++ pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
++ } else {
++ tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
++ *val = tr32(TG3PCI_MEM_WIN_DATA);
++
++ /* Always leave this as zero. */
++ tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
++ }
+ spin_unlock_irqrestore(&tp->indirect_lock, flags);
+ }
+
+@@ -523,6 +534,9 @@
+ if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
+ (tp->hw_status->status & SD_STATUS_UPDATED))
+ tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
++ else
++ tw32(HOSTCC_MODE, tp->coalesce_mode |
++ (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
+ }
+
+ static void tg3_enable_ints(struct tg3 *tp)
+@@ -534,6 +548,9 @@
+ (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
+ tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
+ (tp->last_tag << 24));
++ if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
++ tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
++ (tp->last_tag << 24));
+ tg3_cond_int(tp);
+ }
+
+@@ -560,7 +577,7 @@
+ /* tg3_restart_ints
+ * similar to tg3_enable_ints, but it accurately determines whether there
+ * is new work pending and can return without flushing the PIO write
+- * which reenables interrupts
++ * which reenables interrupts
+ */
+ static void tg3_restart_ints(struct tg3 *tp)
+ {
+@@ -649,7 +666,7 @@
+ frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
+ MI_COM_REG_ADDR_MASK);
+ frame_val |= (MI_COM_CMD_READ | MI_COM_START);
+-
++
+ tw32_f(MAC_MI_COM, frame_val);
+
+ loops = PHY_BUSY_LOOPS;
+@@ -685,6 +702,10 @@
+ unsigned int loops;
+ int ret;
+
++ if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
++ (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
++ return 0;
++
+ if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
+ tw32_f(MAC_MI_MODE,
+ (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
+@@ -697,7 +718,7 @@
+ MI_COM_REG_ADDR_MASK);
+ frame_val |= (val & MI_COM_DATA_MASK);
+ frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
+-
++
+ tw32_f(MAC_MI_COM, frame_val);
+
+ loops = PHY_BUSY_LOOPS;
+@@ -724,6 +745,44 @@
+ return ret;
+ }
+
++static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
++{
++ u32 phy;
++
++ if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
++ (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
++ return;
++
++ if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
++ u32 ephy;
++
++ if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &ephy)) {
++ tg3_writephy(tp, MII_TG3_EPHY_TEST,
++ ephy | MII_TG3_EPHY_SHADOW_EN);
++ if (!tg3_readphy(tp, MII_TG3_EPHYTST_MISCCTRL, &phy)) {
++ if (enable)
++ phy |= MII_TG3_EPHYTST_MISCCTRL_MDIX;
++ else
++ phy &= ~MII_TG3_EPHYTST_MISCCTRL_MDIX;
++ tg3_writephy(tp, MII_TG3_EPHYTST_MISCCTRL, phy);
++ }
++ tg3_writephy(tp, MII_TG3_EPHY_TEST, ephy);
++ }
++ } else {
++ phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
++ MII_TG3_AUXCTL_SHDWSEL_MISC;
++ if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
++ !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
++ if (enable)
++ phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
++ else
++ phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
++ phy |= MII_TG3_AUXCTL_MISC_WREN;
++ tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
++ }
++ }
++}
++
+ static void tg3_phy_set_wirespeed(struct tg3 *tp)
+ {
+ u32 val;
+@@ -948,6 +1007,8 @@
+ return err;
+ }
+
++static void tg3_link_report(struct tg3 *);
++
+ /* This will reset the tigon3 PHY if there is no valid
+ * link unless the FORCE argument is non-zero.
+ */
+@@ -956,11 +1017,23 @@
+ u32 phy_status;
+ int err;
+
++ if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
++ u32 val;
++
++ val = tr32(GRC_MISC_CFG);
++ tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
++ udelay(40);
++ }
+ err = tg3_readphy(tp, MII_BMSR, &phy_status);
+ err |= tg3_readphy(tp, MII_BMSR, &phy_status);
+ if (err != 0)
+ return -EBUSY;
+
++ if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
++ netif_carrier_off(tp->dev);
++ tg3_link_report(tp);
++ }
++
+ if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
+ GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
+ GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
+@@ -997,6 +1070,17 @@
+ tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
+ tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
+ }
++ else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
++ tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
++ tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
++ if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
++ tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
++ tg3_writephy(tp, MII_TG3_TEST1,
++ MII_TG3_TEST1_TRIM_EN | 0x4);
++ } else
++ tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
++ tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
++ }
+ /* Set Extended packet length bit (bit 14) on all chips that */
+ /* support jumbo frames */
+ if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
+@@ -1022,6 +1106,12 @@
+ phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
+ }
+
++ if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
++ /* adjust output voltage */
++ tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
++ }
++
++ tg3_phy_toggle_automdix(tp, 1);
+ tg3_phy_set_wirespeed(tp);
+ return 0;
+ }
+@@ -1030,7 +1120,7 @@
+ {
+ struct tg3 *tp_peer = tp;
+
+- if ((tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) != 0)
++ if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
+ return;
+
+ if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
+@@ -1038,9 +1128,11 @@
+ struct net_device *dev_peer;
+
+ dev_peer = pci_get_drvdata(tp->pdev_peer);
++ /* remove_one() may have been run on the peer. */
+ if (!dev_peer)
+- BUG();
+- tp_peer = netdev_priv(dev_peer);
++ tp_peer = tp;
++ else
++ tp_peer = netdev_priv(dev_peer);
+ }
+
+ if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
+@@ -1120,6 +1212,19 @@
+ }
+ }
+
++static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
++{
++ if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
++ return 1;
++ else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
++ if (speed != SPEED_10)
++ return 1;
++ } else if (speed == SPEED_10)
++ return 1;
++
++ return 0;
++}
++
+ static int tg3_setup_phy(struct tg3 *, int);
+
+ #define RESET_KIND_SHUTDOWN 0
+@@ -1131,7 +1236,47 @@
+ static int tg3_nvram_lock(struct tg3 *);
+ static void tg3_nvram_unlock(struct tg3 *);
+
+-static int tg3_set_power_state(struct tg3 *tp, int state)
++static void tg3_power_down_phy(struct tg3 *tp)
++{
++ if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
++ if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
++ u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
<<Diff was trimmed, longer than 597 lines>>
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