SOURCES: quake3-vm_powerpc-Makefile.patch (NEW), quake3-vm_powerpc.patch (N...
sparky
sparky at pld-linux.org
Fri Oct 24 17:58:16 CEST 2008
Author: sparky Date: Fri Oct 24 15:58:16 2008 GMT
Module: SOURCES Tag: HEAD
---- Log message:
- ppc and ppc64 jit compiler
http://bugzilla.icculus.org/show_bug.cgi?id=3796
---- Files affected:
SOURCES:
quake3-vm_powerpc-Makefile.patch (NONE -> 1.1) (NEW), quake3-vm_powerpc.patch (NONE -> 1.1) (NEW)
---- Diffs:
================================================================
Index: SOURCES/quake3-vm_powerpc-Makefile.patch
diff -u /dev/null SOURCES/quake3-vm_powerpc-Makefile.patch:1.1
--- /dev/null Fri Oct 24 17:58:16 2008
+++ SOURCES/quake3-vm_powerpc-Makefile.patch Fri Oct 24 17:58:10 2008
@@ -0,0 +1,66 @@
+Index: Makefile
+===================================================================
+--- Makefile (revision 1474)
++++ Makefile (working copy)
+@@ -67,6 +67,9 @@
+ ifeq ($(COMPILE_ARCH),powerpc)
+ COMPILE_ARCH=ppc
+ endif
++ifeq ($(COMPILE_ARCH),powerpc64)
++ COMPILE_ARCH=ppc64
++endif
+
+ ifndef ARCH
+ ARCH=$(COMPILE_ARCH)
+@@ -272,10 +275,14 @@
+ else
+ ifeq ($(ARCH),ppc)
+ BASE_CFLAGS += -maltivec
+- HAVE_VM_COMPILED=false
++ HAVE_VM_COMPILED=true
+ endif
++ ifeq ($(ARCH),ppc64)
++ BASE_CFLAGS += -maltivec
++ HAVE_VM_COMPILED=true
+ endif
+ endif
++ endif
+
+ ifneq ($(HAVE_VM_COMPILED),true)
+ BASE_CFLAGS += -DNO_VM_COMPILED
+@@ -345,6 +352,9 @@
+ BASE_CFLAGS += -faltivec
+ OPTIMIZE += -O3
+ endif
++ ifeq ($(ARCH),ppc64)
++ BASE_CFLAGS += -faltivec
++ endif
+ ifeq ($(ARCH),i386)
+ OPTIMIZE += -march=prescott -mfpmath=sse
+ # x86 vm will crash without -mstackrealign since MMX instructions will be
+@@ -1425,8 +1435,11 @@
+ Q3OBJ += $(B)/client/vm_x86_64.o $(B)/client/vm_x86_64_assembler.o
+ endif
+ ifeq ($(ARCH),ppc)
+- Q3OBJ += $(B)/client/vm_ppc.o
++ Q3OBJ += $(B)/client/vm_powerpc.o $(B)/client/vm_powerpc_asm.o
+ endif
++ ifeq ($(ARCH),ppc64)
++ Q3OBJ += $(B)/client/vm_powerpc.o $(B)/client/vm_powerpc_asm.o
++ endif
+ endif
+
+ ifeq ($(PLATFORM),mingw32)
+@@ -1566,8 +1579,11 @@
+ Q3DOBJ += $(B)/ded/vm_x86_64.o $(B)/client/vm_x86_64_assembler.o
+ endif
+ ifeq ($(ARCH),ppc)
+- Q3DOBJ += $(B)/ded/vm_ppc.o
++ Q3DOBJ += $(B)/ded/vm_powerpc.o $(B)/ded/vm_powerpc_asm.o
+ endif
++ ifeq ($(ARCH),ppc64)
++ Q3DOBJ += $(B)/ded/vm_powerpc.o $(B)/ded/vm_powerpc_asm.o
++ endif
+ endif
+
+ ifeq ($(PLATFORM),mingw32)
================================================================
Index: SOURCES/quake3-vm_powerpc.patch
diff -u /dev/null SOURCES/quake3-vm_powerpc.patch:1.1
--- /dev/null Fri Oct 24 17:58:17 2008
+++ SOURCES/quake3-vm_powerpc.patch Fri Oct 24 17:58:10 2008
@@ -0,0 +1,4158 @@
+Index: code/qcommon/vm_powerpc_asm.c
+===================================================================
+--- code/qcommon/vm_powerpc_asm.c (revision 0)
++++ code/qcommon/vm_powerpc_asm.c (revision 0)
+@@ -0,0 +1,1908 @@
++/*
++===========================================================================
++Copyright (C) 2008 Przemyslaw Iskra <sparky at pld-linux.org>
++
++This file is part of Quake III Arena source code.
++
++Quake III Arena source code is free software; you can redistribute it
++and/or modify it under the terms of the GNU General Public License as
++published by the Free Software Foundation; either version 2 of the License,
++or (at your option) any later version.
++
++Quake III Arena source code is distributed in the hope that it will be
++useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
++MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++GNU General Public License for more details.
++
++You should have received a copy of the GNU General Public License
++along with Quake III Arena source code; if not, write to the Free Software
++Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++===========================================================================
++
++ * File includes code from GNU binutils, exactly:
++ * - include/opcode/ppc.h - licensed under GPL v1 or later
++ * - opcodes/ppc-opc.c - licensed under GPL v2 or later
++ *
++ * ppc.h -- Header file for PowerPC opcode table
++ * Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
++ * 2007 Free Software Foundation, Inc.
++ * Written by Ian Lance Taylor, Cygnus Suppor
++ *
++ * This file is part of GDB, GAS, and the GNU binutils.
++ *
++ * ppc-opc.c -- PowerPC opcode list
++ * Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004,
++ * 2005, 2006, 2007 Free Software Foundation, Inc.
++ * Written by Ian Lance Taylor, Cygnus Support
++ *
++ * This file is part of GDB, GAS, and the GNU binutils.
++ *
++ */
++
++#include "vm_powerpc_asm.h"
++
++#include <string.h>
++#include <stdio.h>
++#include <inttypes.h>
++
++/* return nop on error */
++#define ASM_ERROR_OPC (0x60000000)
++
++/*
++ * BEGIN OF ppc.h
++ */
++
++#define ppc_cpu_t int
++
++struct powerpc_opcode
++{
++ const char *name;
++ unsigned long opcode;
++ unsigned long mask;
++ ppc_cpu_t flags;
++ unsigned char operands[8];
++};
++
++static const struct powerpc_opcode powerpc_opcodes[];
++static const int powerpc_num_opcodes;
++
++#define PPC_OPCODE_PPC 1
++#define PPC_OPCODE_POWER 2
++#define PPC_OPCODE_POWER2 4
++#define PPC_OPCODE_32 8
++#define PPC_OPCODE_64 0x10
++#define PPC_OPCODE_601 0x20
++#define PPC_OPCODE_COMMON 0x40
++#define PPC_OPCODE_ANY 0x80
++#define PPC_OPCODE_64_BRIDGE 0x100
++#define PPC_OPCODE_ALTIVEC 0x200
++#define PPC_OPCODE_403 0x400
++#define PPC_OPCODE_BOOKE 0x800
++#define PPC_OPCODE_BOOKE64 0x1000
++#define PPC_OPCODE_440 0x2000
++#define PPC_OPCODE_POWER4 0x4000
++#define PPC_OPCODE_NOPOWER4 0x8000
++#define PPC_OPCODE_CLASSIC 0x10000
++#define PPC_OPCODE_SPE 0x20000
++#define PPC_OPCODE_ISEL 0x40000
++#define PPC_OPCODE_EFS 0x80000
++#define PPC_OPCODE_BRLOCK 0x100000
++#define PPC_OPCODE_PMR 0x200000
++#define PPC_OPCODE_CACHELCK 0x400000
++#define PPC_OPCODE_RFMCI 0x800000
++#define PPC_OPCODE_POWER5 0x1000000
++#define PPC_OPCODE_E300 0x2000000
++#define PPC_OPCODE_POWER6 0x4000000
++#define PPC_OPCODE_CELL 0x8000000
++#define PPC_OPCODE_PPCPS 0x10000000
++#define PPC_OPCODE_E500MC 0x20000000
++#define PPC_OPCODE_405 0x40000000
++#define PPC_OPCODE_VSX 0x80000000
++
++#define PPC_OP(i) (((i) >> 26) & 0x3f)
++
++struct powerpc_operand
++{
++ unsigned int bitm;
++ int shift;
++ unsigned long (*insert)
++ (unsigned long, long, int, const char **);
++ long (*extract) (unsigned long, int, int *);
++ unsigned long flags;
++};
++
++static const struct powerpc_operand powerpc_operands[];
++static const unsigned int num_powerpc_operands;
++
++#define PPC_OPERAND_SIGNED (0x1)
++#define PPC_OPERAND_SIGNOPT (0x2)
++#define PPC_OPERAND_FAKE (0x4)
++#define PPC_OPERAND_PARENS (0x8)
++#define PPC_OPERAND_CR (0x10)
++#define PPC_OPERAND_GPR (0x20)
++#define PPC_OPERAND_GPR_0 (0x40)
++#define PPC_OPERAND_FPR (0x80)
++#define PPC_OPERAND_RELATIVE (0x100)
++#define PPC_OPERAND_ABSOLUTE (0x200)
++#define PPC_OPERAND_OPTIONAL (0x400)
++#define PPC_OPERAND_NEXT (0x800)
++#define PPC_OPERAND_NEGATIVE (0x1000)
++#define PPC_OPERAND_VR (0x2000)
++#define PPC_OPERAND_DS (0x4000)
++#define PPC_OPERAND_DQ (0x8000)
++#define PPC_OPERAND_PLUS1 (0x10000)
++#define PPC_OPERAND_FSL (0x20000)
++#define PPC_OPERAND_FCR (0x40000)
++#define PPC_OPERAND_UDI (0x80000)
++#define PPC_OPERAND_VSR (0x100000)
++
++/*
++ * END OF ppc.h
++ */
++
++#define PPC_DEST_ARCH PPC_OPCODE_PPC
++
++ppc_instruction_t
++asm_instruction( powerpc_iname_t sname, const int argc, const long int *argv )
++{
++ const char *errmsg = NULL;
++ const char *name;
++ unsigned long int ret;
++ const struct powerpc_opcode *opcode = NULL;
++ int argi, argj;
++
++ opcode = &powerpc_opcodes[ sname ];
++ name = opcode->name;
++
++ if ( ! opcode ) {
++ printf( "Can't find opcode %d\n", sname );
++ return ASM_ERROR_OPC;
++ }
++ if ( ( opcode->flags & PPC_DEST_ARCH ) != PPC_DEST_ARCH ) {
++ printf( "opcode %s not defined for this arch\n", name );
++ return ASM_ERROR_OPC;
++ }
++
++ ret = opcode->opcode;
++
++ argi = argj = 0;
++ while ( opcode->operands[ argi ] != 0 ) {
++ long int op = 0;
++ const struct powerpc_operand *operand = &powerpc_operands[ opcode->operands[ argi ] ];
++
++ if ( ! (operand->flags & PPC_OPERAND_FAKE) ) {
++ if ( argj >= argc ) {
++ printf( "Not enough arguments for %s, got %d\n", name, argc );
++ return ASM_ERROR_OPC;
++ }
++
++ op = argv[ argj++ ];
++ }
++
++ if ( operand->insert ) {
++ errmsg = NULL;
++ ret = operand->insert( ret, op, PPC_DEST_ARCH, &errmsg );
++ if ( errmsg ) {
++ printf( "%s: error while inserting operand %d (0x%.2lx): %s\n",
++ name, argi, op, errmsg );
++ }
++ } else {
++ unsigned long int opu = *(unsigned long int *)&op;
++ unsigned long int bitm = operand->bitm;
++ unsigned long int bitm_full = bitm | ( bitm & 1 ? 0 : 0xf );
++
++ if ( operand->flags & PPC_OPERAND_SIGNED ) {
++ bitm_full >>= 1;
++
++ if ( ( opu & ~bitm_full ) != 0 && ( opu | bitm_full ) != -1 )
++ printf( "%s: signed operand nr.%d to wide. op: %.8lx, mask: %.8lx\n",
++ name, argi, opu, bitm );
++ } else {
++ if ( ( opu & ~bitm_full ) != 0 )
++ printf( "%s: unsigned operand nr.%d to wide. op: %.8lx, mask: %.8lx\n",
++ name, argi, opu, bitm );
++ }
++ if ( (bitm & 1) == 0 ) {
++ if ( opu & 0xf & ~bitm )
++ printf( "%s: operand nr.%d not aligned correctly. op: %.8lx, mask: %.8lx\n",
++ name, argi, opu, bitm );
++ }
++
++ ret |= ( op & operand->bitm ) << operand->shift;
++ }
++ argi++;
++ }
++ if ( argc > argj ) {
++ printf( "Too many arguments for %s, got %d\n", name, argc );
++ return ASM_ERROR_OPC;
++ }
++
++ return ret;
++}
++
++
++/*
++ * BEGIN OF ppc-opc.c
++ */
++
++#define ATTRIBUTE_UNUSED
++#define _(x) (x)
++
++/* Local insertion and extraction functions. */
++
++static unsigned long insert_bat (unsigned long, long, int, const char **);
++static long extract_bat (unsigned long, int, int *);
++static unsigned long insert_bba (unsigned long, long, int, const char **);
++static long extract_bba (unsigned long, int, int *);
++static unsigned long insert_bdm (unsigned long, long, int, const char **);
++static long extract_bdm (unsigned long, int, int *);
++static unsigned long insert_bdp (unsigned long, long, int, const char **);
++static long extract_bdp (unsigned long, int, int *);
++static unsigned long insert_bo (unsigned long, long, int, const char **);
++static long extract_bo (unsigned long, int, int *);
++static unsigned long insert_boe (unsigned long, long, int, const char **);
++static long extract_boe (unsigned long, int, int *);
++static unsigned long insert_fxm (unsigned long, long, int, const char **);
++static long extract_fxm (unsigned long, int, int *);
++static unsigned long insert_mbe (unsigned long, long, int, const char **);
++static long extract_mbe (unsigned long, int, int *);
++static unsigned long insert_mb6 (unsigned long, long, int, const char **);
++static long extract_mb6 (unsigned long, int, int *);
++static long extract_nb (unsigned long, int, int *);
++static unsigned long insert_nsi (unsigned long, long, int, const char **);
++static long extract_nsi (unsigned long, int, int *);
++static unsigned long insert_ral (unsigned long, long, int, const char **);
++static unsigned long insert_ram (unsigned long, long, int, const char **);
++static unsigned long insert_raq (unsigned long, long, int, const char **);
++static unsigned long insert_ras (unsigned long, long, int, const char **);
++static unsigned long insert_rbs (unsigned long, long, int, const char **);
++static long extract_rbs (unsigned long, int, int *);
++static unsigned long insert_sh6 (unsigned long, long, int, const char **);
++static long extract_sh6 (unsigned long, int, int *);
++static unsigned long insert_spr (unsigned long, long, int, const char **);
++static long extract_spr (unsigned long, int, int *);
++static unsigned long insert_sprg (unsigned long, long, int, const char **);
++static long extract_sprg (unsigned long, int, int *);
++static unsigned long insert_tbr (unsigned long, long, int, const char **);
++static long extract_tbr (unsigned long, int, int *);
++
++/* The operands table.
++
++ The fields are bitm, shift, insert, extract, flags.
++
++ We used to put parens around the various additions, like the one
++ for BA just below. However, that caused trouble with feeble
++ compilers with a limit on depth of a parenthesized expression, like
++ (reportedly) the compiler in Microsoft Developer Studio 5. So we
++ omit the parens, since the macros are never used in a context where
++ the addition will be ambiguous. */
++
++static const struct powerpc_operand powerpc_operands[] =
++{
++ /* The zero index is used to indicate the end of the list of
++ operands. */
++#define UNUSED 0
++ { 0, 0, NULL, NULL, 0 },
++
++ /* The BA field in an XL form instruction. */
++#define BA UNUSED + 1
++ /* The BI field in a B form or XL form instruction. */
++#define BI BA
++#define BI_MASK (0x1f << 16)
++ { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR },
++
++ /* The BA field in an XL form instruction when it must be the same
++ as the BT field in the same instruction. */
++#define BAT BA + 1
++ { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
++
++ /* The BB field in an XL form instruction. */
++#define BB BAT + 1
++#define BB_MASK (0x1f << 11)
++ { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR },
++
++ /* The BB field in an XL form instruction when it must be the same
++ as the BA field in the same instruction. */
++#define BBA BB + 1
++ { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
++
++ /* The BD field in a B form instruction. The lower two bits are
++ forced to zero. */
++#define BD BBA + 1
++ { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
++
++ /* The BD field in a B form instruction when absolute addressing is
++ used. */
++#define BDA BD + 1
++ { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
++
++ /* The BD field in a B form instruction when the - modifier is used.
++ This sets the y bit of the BO field appropriately. */
++#define BDM BDA + 1
++ { 0xfffc, 0, insert_bdm, extract_bdm,
++ PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
++
++ /* The BD field in a B form instruction when the - modifier is used
++ and absolute address is used. */
++#define BDMA BDM + 1
++ { 0xfffc, 0, insert_bdm, extract_bdm,
++ PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
++
++ /* The BD field in a B form instruction when the + modifier is used.
++ This sets the y bit of the BO field appropriately. */
++#define BDP BDMA + 1
++ { 0xfffc, 0, insert_bdp, extract_bdp,
++ PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
++
++ /* The BD field in a B form instruction when the + modifier is used
++ and absolute addressing is used. */
++#define BDPA BDP + 1
++ { 0xfffc, 0, insert_bdp, extract_bdp,
++ PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
++
++ /* The BF field in an X or XL form instruction. */
++#define BF BDPA + 1
++ /* The CRFD field in an X form instruction. */
++#define CRFD BF
++ { 0x7, 23, NULL, NULL, PPC_OPERAND_CR },
++
++ /* The BF field in an X or XL form instruction. */
++#define BFF BF + 1
++ { 0x7, 23, NULL, NULL, 0 },
++
++ /* An optional BF field. This is used for comparison instructions,
++ in which an omitted BF field is taken as zero. */
++#define OBF BFF + 1
++ { 0x7, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
++
++ /* The BFA field in an X or XL form instruction. */
++#define BFA OBF + 1
++ { 0x7, 18, NULL, NULL, PPC_OPERAND_CR },
++
++ /* The BO field in a B form instruction. Certain values are
++ illegal. */
++#define BO BFA + 1
++#define BO_MASK (0x1f << 21)
++ { 0x1f, 21, insert_bo, extract_bo, 0 },
++
++ /* The BO field in a B form instruction when the + or - modifier is
++ used. This is like the BO field, but it must be even. */
++#define BOE BO + 1
++ { 0x1e, 21, insert_boe, extract_boe, 0 },
++
++#define BH BOE + 1
++ { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
++
++ /* The BT field in an X or XL form instruction. */
++#define BT BH + 1
++ { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR },
++
++ /* The condition register number portion of the BI field in a B form
++ or XL form instruction. This is used for the extended
++ conditional branch mnemonics, which set the lower two bits of the
++ BI field. This field is optional. */
++#define CR BT + 1
++ { 0x7, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
++
++ /* The CRB field in an X form instruction. */
++#define CRB CR + 1
++ /* The MB field in an M form instruction. */
++#define MB CRB
++#define MB_MASK (0x1f << 6)
++ { 0x1f, 6, NULL, NULL, 0 },
++
++ /* The CRFS field in an X form instruction. */
++#define CRFS CRB + 1
++ { 0x7, 0, NULL, NULL, PPC_OPERAND_CR },
++
++ /* The CT field in an X form instruction. */
++#define CT CRFS + 1
++ /* The MO field in an mbar instruction. */
++#define MO CT
++ { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
++
++ /* The D field in a D form instruction. This is a displacement off
++ a register, and implies that the next operand is a register in
++ parentheses. */
++#define D CT + 1
++ { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
++
++ /* The DE field in a DE form instruction. This is like D, but is 12
++ bits only. */
++#define DE D + 1
++ { 0xfff, 4, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
++
++ /* The DES field in a DES form instruction. This is like DS, but is 14
++ bits only (12 stored.) */
++#define DES DE + 1
++ { 0x3ffc, 2, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
++
++ /* The DQ field in a DQ form instruction. This is like D, but the
++ lower four bits are forced to zero. */
++#define DQ DES + 1
++ { 0xfff0, 0, NULL, NULL,
++ PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
++
++ /* The DS field in a DS form instruction. This is like D, but the
++ lower two bits are forced to zero. */
++#define DS DQ + 1
++ { 0xfffc, 0, NULL, NULL,
++ PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
++
++ /* The E field in a wrteei instruction. */
++#define E DS + 1
++ { 0x1, 15, NULL, NULL, 0 },
++
++ /* The FL1 field in a POWER SC form instruction. */
++#define FL1 E + 1
++ /* The U field in an X form instruction. */
++#define U FL1
++ { 0xf, 12, NULL, NULL, 0 },
++
++ /* The FL2 field in a POWER SC form instruction. */
++#define FL2 FL1 + 1
++ { 0x7, 2, NULL, NULL, 0 },
++
++ /* The FLM field in an XFL form instruction. */
++#define FLM FL2 + 1
++ { 0xff, 17, NULL, NULL, 0 },
++
++ /* The FRA field in an X or A form instruction. */
++#define FRA FLM + 1
++#define FRA_MASK (0x1f << 16)
++ { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR },
++
++ /* The FRB field in an X or A form instruction. */
++#define FRB FRA + 1
++#define FRB_MASK (0x1f << 11)
++ { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR },
++
++ /* The FRC field in an A form instruction. */
++#define FRC FRB + 1
++#define FRC_MASK (0x1f << 6)
++ { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR },
++
++ /* The FRS field in an X form instruction or the FRT field in a D, X
++ or A form instruction. */
++#define FRS FRC + 1
++#define FRT FRS
++ { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR },
++
++ /* The FXM field in an XFX instruction. */
++#define FXM FRS + 1
++ { 0xff, 12, insert_fxm, extract_fxm, 0 },
++
++ /* Power4 version for mfcr. */
++#define FXM4 FXM + 1
++ { 0xff, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL },
++
++ /* The L field in a D or X form instruction. */
++#define L FXM4 + 1
++ { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
++
++ /* The LEV field in a POWER SVC form instruction. */
++#define SVC_LEV L + 1
++ { 0x7f, 5, NULL, NULL, 0 },
++
++ /* The LEV field in an SC form instruction. */
++#define LEV SVC_LEV + 1
++ { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL },
++
++ /* The LI field in an I form instruction. The lower two bits are
++ forced to zero. */
++#define LI LEV + 1
++ { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
++
++ /* The LI field in an I form instruction when used as an absolute
++ address. */
++#define LIA LI + 1
++ { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
++
++ /* The LS field in an X (sync) form instruction. */
++#define LS LIA + 1
++ { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
++
++ /* The ME field in an M form instruction. */
++#define ME LS + 1
++#define ME_MASK (0x1f << 1)
++ { 0x1f, 1, NULL, NULL, 0 },
++
++ /* The MB and ME fields in an M form instruction expressed a single
++ operand which is a bitmask indicating which bits to select. This
++ is a two operand form using PPC_OPERAND_NEXT. See the
++ description in opcode/ppc.h for what this means. */
++#define MBE ME + 1
<<Diff was trimmed, longer than 597 lines>>
More information about the pld-cvs-commit
mailing list