[packages/kernel] drop "atheros disallow retrain" patch in favor of pcie_aspm=off workaround
atler
atler at pld-linux.org
Sat Sep 20 21:37:41 CEST 2025
commit 414b3a2f6ca54e40620c8206b85f8f72e3ef3096
Author: Jan Palus <atler at pld-linux.org>
Date: Sat Sep 20 17:34:59 2025 +0200
drop "atheros disallow retrain" patch in favor of pcie_aspm=off workaround
as suggested/discussed with Klaus Kudielka
atheros-disallow-retrain-nongen1-pcie.patch | 292 ----------------------------
kernel.spec | 2 -
2 files changed, 294 deletions(-)
---
diff --git a/kernel.spec b/kernel.spec
index f7999fce..4fa420df 100644
--- a/kernel.spec
+++ b/kernel.spec
@@ -175,7 +175,6 @@ Patch7000: kernel-inittmpfs.patch
# ARM only
Patch8000: rpi-sound.patch
Patch8001: kernel-pinebook-pro.patch
-Patch8002: atheros-disallow-retrain-nongen1-pcie.patch
Patch8004: ath-regd.patch
Patch8005: rkvdec-hevc.patch
# Patch8005-md5: c357a58f19f1466d89ec8ef008ce7e34
@@ -579,7 +578,6 @@ cd linux-%{basever}
%ifarch %{arm} aarch64
%patch -P8000 -p1
%patch -P8001 -p1
-%patch -P8002 -p1
%patch -P8004 -p1
%patch -P8005 -p1
%endif
diff --git a/atheros-disallow-retrain-nongen1-pcie.patch b/atheros-disallow-retrain-nongen1-pcie.patch
deleted file mode 100644
index 0681c2a8..00000000
--- a/atheros-disallow-retrain-nongen1-pcie.patch
+++ /dev/null
@@ -1,292 +0,0 @@
-From mboxrd at z Thu Jan 1 00:00:00 1970
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- id 09BEF79D; Wed, 5 May 2021 18:34:57 +0200 (CEST)
-From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali at kernel.org>
-To: Bjorn Helgaas <bhelgaas at google.com>,
- Kalle Valo <kvalo at codeaurora.org>,
- =?UTF-8?q?Toke=20H=C3=B8iland-J=C3=B8rgensen?= <toke at redhat.com>,
- =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel at kernel.org>,
- =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= <kw at linux.com>
-Cc: vtolkm at gmail.com, Rob Herring <robh at kernel.org>,
- Ilias Apalodimas <ilias.apalodimas at linaro.org>,
- Thomas Petazzoni <thomas.petazzoni at bootlin.com>,
- linux-pci at vger.kernel.org, ath10k at lists.infradead.org,
- linux-wireless at vger.kernel.org, linux-kernel at vger.kernel.org
-Subject: [PATCH v3] PCI: Disallow retraining link for Atheros chips on non-Gen1 PCIe bridges
-Date: Wed, 5 May 2021 18:33:57 +0200
-Message-Id: <20210505163357.16012-1-pali at kernel.org>
-X-Mailer: git-send-email 2.20.1
-In-Reply-To: <20210326124326.21163-1-pali at kernel.org>
-References: <20210326124326.21163-1-pali at kernel.org>
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
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-Precedence: bulk
-List-ID: <linux-pci.vger.kernel.org>
-X-Mailing-List: linux-pci at vger.kernel.org
-
-Atheros AR9xxx and QCA9xxx chips have behaviour issues not only after a
-bus reset, but also after doing retrain link, if PCIe bridge is not in
-GEN1 mode (at 2.5 GT/s speed):
-
-- QCA9880 and QCA9890 chips throw a Link Down event and completely
- disappear from the bus and their config space is not accessible
- afterwards.
-
-- QCA9377 chip throws a Link Down event followed by Link Up event, the
- config space is accessible and PCI device ID is correct. But trying to
- access chip's I/O space causes Uncorrected (Non-Fatal) AER error,
- followed by Synchronous external abort 96000210 and Segmentation fault
- of insmod while loading ath10k_pci.ko module.
-
-- AR9390 chip throws a Link Down event followed by Link Up event, config
- space is accessible, but contains nonsense values. PCI device ID is
- 0xABCD which indicates HW bug that chip itself was not able to read
- values from internal EEPROM/OTP.
-
-- AR9287 chip throws also Link Down and Link Up events, also has
- accessible config space containing correct values. But ath9k driver
- fails to initialize card from this state as it is unable to access HW
- registers. This also indicates that the chip iself is not able to read
- values from internal EEPROM/OTP.
-
-These issues related to PCI device ID 0xABCD and to reading internal
-EEPROM/OTP were previously discussed at ath9k-devel mailing list in
-following thread:
-
- https://www.mail-archive.com/ath9k-devel@lists.ath9k.org/msg07529.html
-
-After experiments we've come up with a solution: it seems that Retrain
-link can be called only when using GEN1 PCIe bridge or when PCIe bridge
-link speed is forced to 2.5 GT/s. Applying this workaround fixes all
-mentioned cards.
-
-This issue was reproduced with more cards:
-- Compex WLE900VX (QCA9880 based / device ID 0x003c)
-- QCNFA435 (QCA9377 based / device ID 0x0042)
-- Compex WLE200NX (AR9287 based / device ID 0x002e)
-- "noname" card (QCA9890 based / device ID 0x003c)
-- Wistron NKR-DNXAH1 (AR9390 based / device ID 0x0030)
-on Armada 385 with pci-mvebu.c driver and also on Armada 3720 with
-pci-aardvark.c driver.
-
-To workaround this issue, this change introduces a new PCI quirk called
-PCI_DEV_FLAGS_NO_RETRAIN_LINK_WHEN_NOT_GEN1, which is enabled for all
-Atheros chips with PCI_DEV_FLAGS_NO_BUS_RESET quirk, and also for Atheros
-chip AR9287.
-
-When this quirk is set, kernel disallows triggering PCI_EXP_LNKCTL_RL
-bit in config space of PCIe Bridge in the case when PCIe Bridge is
-capable of higher speed than 2.5 GT/s and this higher speed is already
-allowed. When PCIe Bridge has accessible LNKCTL2 register, we try to
-force target link speed to 2.5 GT/s. After this change it is possible
-to trigger PCI_EXP_LNKCTL_RL bit without issues.
-
-Currently only PCIe ASPM kernel code triggers this PCI_EXP_LNKCTL_RL bit,
-so quirk check is added only into pcie/aspm.c file.
-
-Signed-off-by: Pali Rohár <pali at kernel.org>
-Reported-by: Toke Høiland-Jørgensen <toke at redhat.com>
-Tested-by: Toke Høiland-Jørgensen <toke at redhat.com>
-Tested-by: Marek Behún <kabel at kernel.org>
-BugLink: https://lore.kernel.org/linux-pci/87h7l8axqp.fsf@toke.dk/
-BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=84821
-BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=192441
-BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=209833
-Cc: stable at vger.kernel.org # c80851f6ce63a ("PCI: Add PCI_EXP_LNKCTL2_TLS* macros")
-
----
-Changes since v1:
-* Move whole quirk code into pcie_downgrade_link_to_gen1() function
-* Reformat to 80 chars per line where possible
-* Add quirk also for cards with AR9287 chip (PCI ID 0x002e)
-* Extend commit message description and add information about 0xABCD
-
-Changes since v2:
-* Add quirk also for Atheros QCA9377 chip
----
- drivers/pci/pcie/aspm.c | 44 +++++++++++++++++++++++++++++++++++++++++
- drivers/pci/quirks.c | 39 ++++++++++++++++++++++++++++--------
- include/linux/pci.h | 2 ++
- 3 files changed, 77 insertions(+), 8 deletions(-)
-
---- linux-6.5/drivers/pci/pcie/aspm.c.orig 2023-08-27 23:49:51.000000000 +0200
-+++ linux-6.5/drivers/pci/pcie/aspm.c 2023-08-29 19:04:58.069254559 +0200
-@@ -191,6 +191,44 @@
- link->clkpm_disable = blacklist ? 1 : 0;
- }
-
-+static int pcie_downgrade_link_to_gen1(struct pci_dev *parent)
-+{
-+ u16 reg16;
-+ u32 reg32;
-+ int ret;
-+
-+ /* Check if link is capable of higher speed than 2.5 GT/s */
-+ pcie_capability_read_dword(parent, PCI_EXP_LNKCAP, ®32);
-+ if ((reg32 & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB)
-+ return 0;
-+
-+ /* Check if link speed can be downgraded to 2.5 GT/s */
-+ pcie_capability_read_dword(parent, PCI_EXP_LNKCAP2, ®32);
-+ if (!(reg32 & PCI_EXP_LNKCAP2_SLS_2_5GB)) {
-+ pci_err(parent, "ASPM: Bridge does not support changing Link Speed to 2.5 GT/s\n");
-+ return -EOPNOTSUPP;
-+ }
-+
-+ /* Force link speed to 2.5 GT/s */
-+ ret = pcie_capability_clear_and_set_word(parent, PCI_EXP_LNKCTL2,
-+ PCI_EXP_LNKCTL2_TLS,
-+ PCI_EXP_LNKCTL2_TLS_2_5GT);
-+ if (!ret) {
-+ /* Verify that new value was really set */
-+ pcie_capability_read_word(parent, PCI_EXP_LNKCTL2, ®16);
-+ if ((reg16 & PCI_EXP_LNKCTL2_TLS) != PCI_EXP_LNKCTL2_TLS_2_5GT)
-+ ret = -EINVAL;
-+ }
-+
-+ if (ret) {
-+ pci_err(parent, "ASPM: Changing Target Link Speed to 2.5 GT/s failed: %d\n", ret);
-+ return ret;
-+ }
-+
-+ pci_info(parent, "ASPM: Target Link Speed changed to 2.5 GT/s due to quirk\n");
-+ return 0;
-+}
-+
- /*
- * pcie_aspm_configure_common_clock: check if the 2 ends of a link
- * could use common clock. If they are, configure them to use the
-@@ -257,7 +295,14 @@
- pcie_capability_clear_and_set_word(parent, PCI_EXP_LNKCTL,
- PCI_EXP_LNKCTL_CCC, ccc);
-
-- if (pcie_retrain_link(link->pdev, true)) {
-+ bool skip_retrain = false;
-+ if (link->downstream->dev_flags & PCI_DEV_FLAGS_NO_RETRAIN_LINK_WHEN_NOT_GEN1) {
-+ if (pcie_downgrade_link_to_gen1(parent)) {
-+ pci_err(parent, "ASPM: Retrain Link at higher speed is disallowed by quirk\n");
-+ skip_retrain = true;
-+ }
-+ }
-+ if (!skip_retrain && pcie_retrain_link(link->pdev, true)) {
-
- /* Training failed. Restore common clock configurations */
- pci_err(parent, "ASPM: Could not configure common clock\n");
-diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
-index 653660e3ba9e..4999ad9d08b8 100644
---- a/drivers/pci/quirks.c
-+++ b/drivers/pci/quirks.c
-@@ -3553,31 +3553,55 @@ static void mellanox_check_broken_intx_masking(struct pci_dev *pdev)
- dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;
- }
-
-+static void quirk_no_bus_reset_and_no_retrain_link(struct pci_dev *dev)
-+{
-+ dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET |
-+ PCI_DEV_FLAGS_NO_RETRAIN_LINK_WHEN_NOT_GEN1;
-+}
-+
- /*
- * Some NVIDIA GPU devices do not work with bus reset, SBR needs to be
- * prevented for those affected devices.
- */
- static void quirk_nvidia_no_bus_reset(struct pci_dev *dev)
- {
- if ((dev->device & 0xffc0) == 0x2340)
- quirk_no_bus_reset(dev);
- }
- DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
- quirk_nvidia_no_bus_reset);
-
- /*
-- * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset.
-+ * Atheros AR9xxx and QCA9xxx chips do not behave after a bus reset and also
-+ * after retrain link when PCIe bridge is not in GEN1 mode at 2.5 GT/s speed.
- * The device will throw a Link Down error on AER-capable systems and
- * regardless of AER, config space of the device is never accessible again
- * and typically causes the system to hang or reset when access is attempted.
-+ * Or if config space is accessible again then it contains only dummy values
-+ * like fixed PCI device ID 0xABCD or values not initialized at all.
-+ * Retrain link can be called only when using GEN1 PCIe bridge or when
-+ * PCIe bridge has forced link speed to 2.5 GT/s via PCI_EXP_LNKCTL2 register.
-+ * To reset these cards it is required to do PCIe Warm Reset via PERST# pin.
- * https://lore.kernel.org/r/20140923210318.498dacbd@dualc.maya.org/
-+ * https://lore.kernel.org/r/87h7l8axqp.fsf@toke.dk/
-+ * https://www.mail-archive.com/ath9k-devel@lists.ath9k.org/msg07529.html
- */
--DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset);
--DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset);
--DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset);
--DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset);
--DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset);
--DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003e, quirk_no_bus_reset);
-+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x002e,
-+ quirk_no_bus_reset_and_no_retrain_link);
-+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030,
-+ quirk_no_bus_reset_and_no_retrain_link);
-+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032,
-+ quirk_no_bus_reset_and_no_retrain_link);
-+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033,
-+ quirk_no_bus_reset_and_no_retrain_link);
-+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034,
-+ quirk_no_bus_reset_and_no_retrain_link);
-+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c,
-+ quirk_no_bus_reset_and_no_retrain_link);
-+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003e,
-+ quirk_no_bus_reset_and_no_retrain_link);
-+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0042,
-+ quirk_no_bus_reset_and_no_retrain_link);
-
- /*
- * Root port on some Cavium CN8xxx chips do not successfully complete a bus
-diff --git a/include/linux/pci.h b/include/linux/pci.h
-index 86c799c97b77..fdbf7254e4ab 100644
---- a/include/linux/pci.h
-+++ b/include/linux/pci.h
-@@ -227,6 +227,8 @@ enum pci_dev_flags {
- PCI_DEV_FLAGS_HAS_MSI_MASKING = (__force pci_dev_flags_t) (1 << 12),
- /* Device requires write to PCI_MSIX_ENTRY_DATA before any MSIX reads */
- PCI_DEV_FLAGS_MSIX_TOUCH_ENTRY_DATA_FIRST = (__force pci_dev_flags_t) (1 << 13),
-+ /* Don't Retrain Link for device when bridge is not in GEN1 mode */
-+ PCI_DEV_FLAGS_NO_RETRAIN_LINK_WHEN_NOT_GEN1 = (__force pci_dev_flags_t) (1 << 14),
- };
-
- enum pci_irq_reroute_variant {
---
-2.20.1
-
-
================================================================
---- gitweb:
http://git.pld-linux.org/gitweb.cgi/packages/kernel.git/commitdiff/0ac20805717be41ad52867b27b85f5455a2a59e1
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