SPECS: verilog.spec - alter sources in %prep, so %build and %insta...

[glen]

Author: glen                         Date: Tue Mar  7 23:47:37 2006 GMT
Module: SPECS                         Tag: HEAD
---- Log message:
- alter sources in %prep, so %build and %install can be --short-circuit
- restore rcsid tags

---- Files affected:
SPECS:
   verilog.spec (1.1 -> 1.2) 

---- Diffs:

================================================================
Index: SPECS/verilog.spec
diff -u SPECS/verilog.spec:1.1 SPECS/verilog.spec:1.2
--- SPECS/verilog.spec:1.1	Wed Mar  8 00:29:32 2006
+++ SPECS/verilog.spec	Wed Mar  8 00:47:31 2006
@@ -1,3 +1,4 @@
+# $Revision$, $Date$
 Summary:	Icarus Verilog is Verilog compiler and simulator
 Summary(pl):	Icarus Verilog jest kompilatorem i symulatorem Veriloga
 Name:		verilog
@@ -28,6 +29,9 @@
 %setup -q
 %patch0 -p1
 
+rm -f examples/.cvsignore
+mv tgt-edif/LICENSE.txt LICENSE_edif.txt
+
 %build
 %configure
 
@@ -43,10 +47,8 @@
 %{__make} install \
 	DESTDIR=$RPM_BUILD_ROOT
 
-rm -f examples/.cvsignore
 install -d $RPM_BUILD_ROOT%{_examplesdir}/%{name}-%{version}
 cp -a examples/* $RPM_BUILD_ROOT%{_examplesdir}/%{name}-%{version}
-mv tgt-edif/LICENSE.txt LICENSE_edif.txt
 
 rm -rf $RPM_BUILD_ROOT%{_libdir}/*.a
 
@@ -77,6 +79,9 @@
 All persons listed below can be reached at <cvs_login>@pld-linux.org
 
 $Log$
+Revision 1.2  2006/03/07 23:47:31  glen
+- alter sources in %prep, so %build and %install can be --short-circuit
+- restore rcsid tags
+
 Revision 1.1  2006/03/07 23:29:32  maciek2w
 - initial release
-
================================================================

---- CVS-web:
    http://cvs.pld-linux.org/SPECS/verilog.spec?r1=1.1&r2=1.2&f=u