SOURCES: gcc-ix86-branch.diff - regenerated for gcc-4.4.
pluto
pluto at pld-linux.org
Tue Apr 21 22:53:10 CEST 2009
Author: pluto Date: Tue Apr 21 20:53:10 2009 GMT
Module: SOURCES Tag: HEAD
---- Log message:
- regenerated for gcc-4.4.
---- Files affected:
SOURCES:
gcc-ix86-branch.diff (1.1 -> 1.2)
---- Diffs:
================================================================
Index: SOURCES/gcc-ix86-branch.diff
diff -u SOURCES/gcc-ix86-branch.diff:1.1 SOURCES/gcc-ix86-branch.diff:1.2
--- SOURCES/gcc-ix86-branch.diff:1.1 Tue Mar 31 20:54:19 2009
+++ SOURCES/gcc-ix86-branch.diff Tue Apr 21 22:53:05 2009
@@ -1,1421 +1,3689 @@
-Index: gcc/doc/extend.texi
-===================================================================
---- gcc/doc/extend.texi (.../gcc-4_3-branch) (revision 145062)
-+++ gcc/doc/extend.texi (.../ix86/gcc-4_3-branch) (revision 145364)
-@@ -7962,6 +7962,27 @@
- Generates the @code{popcntq} machine instruction.
- @end table
-
-+The following built-in functions are available when @option{-maes} is
-+used. All of them generate the machine instruction that is part of the
-+name.
-+
-+ at smallexample
-+v2di __builtin_ia32_aesenc128 (v2di, v2di)
-+v2di __builtin_ia32_aesenclast128 (v2di, v2di)
-+v2di __builtin_ia32_aesdec128 (v2di, v2di)
-+v2di __builtin_ia32_aesdeclast128 (v2di, v2di)
-+v2di __builtin_ia32_aeskeygenassist128 (v2di, const int)
-+v2di __builtin_ia32_aesimc128 (v2di)
-+ at end smallexample
-+
-+The following built-in function is available when @option{-mpclmul} is
-+used.
-+
-+ at table @code
-+ at item v2di __builtin_ia32_pclmulqdq128 (v2di, v2di, const int)
-+Generates the @code{pclmulqdq} machine instruction.
-+ at end table
-+
- The following built-in functions are available when @option{-msse4a} is used.
- All of them generate the machine instruction that is part of the name.
-
Index: gcc/doc/invoke.texi
===================================================================
---- gcc/doc/invoke.texi (.../gcc-4_3-branch) (revision 145062)
-+++ gcc/doc/invoke.texi (.../ix86/gcc-4_3-branch) (revision 145364)
-@@ -551,6 +551,7 @@
- -mno-wide-multiply -mrtd -malign-double @gol
- -mpreferred-stack-boundary=@var{num} -mcld -mcx16 -msahf -mrecip @gol
- -mmmx -msse -msse2 -msse3 -mssse3 -msse4.1 -msse4.2 -msse4 @gol
-+-maes -mpclmul @gol
- -msse4a -m3dnow -mpopcnt -mabm -msse5 @gol
- -mthreads -mno-align-stringops -minline-all-stringops @gol
- -mpush-args -maccumulate-outgoing-args -m128bit-long-double @gol
-@@ -10733,6 +10734,10 @@
- @itemx -mno-sse4.2
- @item -msse4
- @itemx -mno-sse4
-+ at item -maes
-+ at itemx -mno-aes
-+ at item -mpclmul
-+ at itemx -mno-pclmul
- @item -msse4a
- @item -mno-sse4a
- @item -msse5
-@@ -10750,8 +10755,8 @@
- @opindex m3dnow
- @opindex mno-3dnow
- These switches enable or disable the use of instructions in the MMX,
--SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4A, SSE5, ABM or 3DNow!@: extended
--instruction sets.
-+SSE, SSE2, SSE3, SSSE3, SSE4.1, AES, PCLMUL, SSE4A, SSE5, ABM or
-+3DNow!@: extended instruction sets.
- These extensions are also available as built-in functions: see
- @ref{X86 Built-in Functions}, for details of the functions enabled and
- disabled by these switches.
-Index: gcc/testsuite/gcc.target/i386/sse-14.c
-===================================================================
---- gcc/testsuite/gcc.target/i386/sse-14.c (.../gcc-4_3-branch) (revision 145062)
-+++ gcc/testsuite/gcc.target/i386/sse-14.c (.../ix86/gcc-4_3-branch) (revision 145364)
-@@ -1,14 +1,15 @@
- /* { dg-do compile } */
--/* { dg-options "-O0 -march=k8 -m3dnow -msse4 -msse5" } */
-+/* { dg-options "-O0 -march=k8 -m3dnow -msse4 -msse5 -maes -mpclmul" } */
-
- /* Test that the intrinsics compile without optimization. All of them are
-- defined as inline functions in {,x,e,p,t,s,a,b}mmintrin.h and mm3dnow.h
-+ defined as inline functions in {,x,e,p,t,s,w,a,b}mmintrin.h and mm3dnow.h
- that reference the proper builtin functions. Defining away "extern" and
- "__inline" results in all of them being compiled as proper functions. */
-
- #define extern
- #define __inline
-
-+#include <wmmintrin.h>
- #include <bmmintrin.h>
- #include <smmintrin.h>
- #include <mm3dnow.h>
-@@ -44,6 +45,10 @@
- test_1x (_mm_extracti_si64, __m128i, __m128i, 1, 1)
- test_2x (_mm_inserti_si64, __m128i, __m128i, __m128i, 1, 1)
-
-+/* wmmintrin.h */
-+test_1 (_mm_aeskeygenassist_si128, __m128i, __m128i, 1)
-+test_2 (_mm_clmulepi64_si128, __m128i, __m128i, __m128i, 1)
-+
- /* smmintrin.h */
- test_2 (_mm_blend_epi16, __m128i, __m128i, __m128i, 1)
- test_2 (_mm_blend_ps, __m128, __m128, __m128, 1)
-Index: gcc/testsuite/gcc.target/i386/i386.exp
-===================================================================
---- gcc/testsuite/gcc.target/i386/i386.exp (.../gcc-4_3-branch) (revision 145062)
-+++ gcc/testsuite/gcc.target/i386/i386.exp (.../ix86/gcc-4_3-branch) (revision 145364)
-@@ -51,6 +51,34 @@
- } "-O2 -msse4.1" ]
+--- gcc/doc/invoke.texi (.../tags/gcc_4_4_0_release) (revision 146537)
++++ gcc/doc/invoke.texi (.../branches/ix86/gcc-4_4-branch) (revision 146537)
+@@ -584,7 +584,7 @@
+ -m96bit-long-double -mregparm=@var{num} -msseregparm @gol
+ -mveclibabi=@var{type} -mpc32 -mpc64 -mpc80 -mstackrealign @gol
+ -momit-leaf-frame-pointer -mno-red-zone -mno-tls-direct-seg-refs @gol
+--mcmodel=@var{code-model} @gol
++-mcmodel=@var{code-model} -mabi=@var{name} @gol
+ -m32 -m64 -mlarge-data-threshold=@var{num} @gol
+ -mfused-madd -mno-fused-madd -msse2avx}
+
+@@ -10959,6 +10959,9 @@
+ @item core2
+ Intel Core2 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3 and SSSE3
+ instruction set support.
++ at item atom
++Intel Atom CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3 and SSSE3
++instruction set support.
+ @item k6
+ AMD K6 CPU with MMX instruction set support.
+ @item k6-2, k6-3
+@@ -11394,6 +11397,16 @@
+ @option{-funsafe-math-optimizations} have to be enabled. A SVML or ACML ABI
+ compatible library will have to be specified at link time.
+
++ at item -mabi=@var{name}
++ at opindex mabi
++Generate code for the specified calling convention. Permissible values
++are: @samp{sysv} for the ABI used on GNU/Linux and other systems and
++ at samp{ms} for the Microsoft ABI. The default is to use the Microsoft
++ABI when targeting Windows. On all other systems, the default is the
++SYSV ABI. You can control this behavior for a specific function by
++using the function attribute @samp{ms_abi}/@samp{sysv_abi}.
++ at xref{Function Attributes}.
++
+ @item -mpush-args
+ @itemx -mno-push-args
+ @opindex mpush-args
+Index: gcc/doc/md.texi
+===================================================================
+--- gcc/doc/md.texi (.../tags/gcc_4_4_0_release) (revision 146537)
++++ gcc/doc/md.texi (.../branches/ix86/gcc-4_4-branch) (revision 146537)
+@@ -7506,6 +7506,11 @@
+ recognize complicated bypasses, e.g.@: when the consumer is only an address
+ of insn @samp{store} (not a stored value).
+
++If there are more one bypass with the same output and input insns, the
++chosen bypass is the first bypass with a guard in description whose
++guard function returns nonzero. If there is no such bypass, then
++bypass without the guard function is chosen.
++
+ @findex exclusion_set
+ @findex presence_set
+ @findex final_presence_set
+Index: gcc/genautomata.c
+===================================================================
+--- gcc/genautomata.c (.../tags/gcc_4_4_0_release) (revision 146537)
++++ gcc/genautomata.c (.../branches/ix86/gcc-4_4-branch) (revision 146537)
+@@ -1,5 +1,5 @@
+ /* Pipeline hazard description translator.
+- Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008
++ Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009
+ Free Software Foundation, Inc.
+
+ Written by Vladimir Makarov <vmakarov at redhat.com>
+@@ -22,21 +22,25 @@
+
+ /* References:
+
+- 1. Detecting pipeline structural hazards quickly. T. Proebsting,
++ 1. The finite state automaton based pipeline hazard recognizer and
++ instruction scheduler in GCC. V. Makarov. Proceedings of GCC
++ summit, 2003.
++
++ 2. Detecting pipeline structural hazards quickly. T. Proebsting,
+ C. Fraser. Proceedings of ACM SIGPLAN-SIGACT Symposium on
+ Principles of Programming Languages, pages 280--286, 1994.
+
+ This article is a good start point to understand usage of finite
+ state automata for pipeline hazard recognizers. But I'd
+- recommend the 2nd article for more deep understanding.
++ recommend the 1st and 3rd article for more deep understanding.
+
+- 2. Efficient Instruction Scheduling Using Finite State Automata:
++ 3. Efficient Instruction Scheduling Using Finite State Automata:
+ V. Bala and N. Rubin, Proceedings of MICRO-28. This is the best
+ article about usage of finite state automata for pipeline hazard
+ recognizers.
+
+- The current implementation is different from the 2nd article in the
+- following:
++ The current implementation is described in the 1st article and it
++ is different from the 3rd article in the following:
+
+ 1. New operator `|' (alternative) is permitted in functional unit
+ reservation which can be treated deterministically and
+@@ -463,7 +467,10 @@
+ insn. */
+ int insn_num;
+ /* The following field value is list of bypasses in which given insn
+- is output insn. */
++ is output insn. Bypasses with the same input insn stay one after
++ another in the list in the same order as their occurrences in the
++ description but the bypass without a guard stays always the last
++ in a row of bypasses with the same input insn. */
+ struct bypass_decl *bypass_list;
+
+ /* The following fields are defined by automaton generator. */
+@@ -2367,18 +2374,67 @@
}
-+# Return 1 if aes instructions can be compiled.
-+proc check_effective_target_aes { } {
-+ return [check_no_compiler_messages aes object {
-+ typedef long long __m128i __attribute__ ((__vector_size__ (16)));
-+ typedef long long __v2di __attribute__ ((__vector_size__ (16)));
-+
-+ __m128i _mm_aesimc_si128 (__m128i __X)
-+ {
-+ return (__m128i) __builtin_ia32_aesimc128 ((__v2di)__X);
-+ }
-+ } "-O2 -maes" ]
-+}
-+
-+# Return 1 if pclmul instructions can be compiled.
-+proc check_effective_target_pclmul { } {
-+ return [check_no_compiler_messages pclmul object {
-+ typedef long long __m128i __attribute__ ((__vector_size__ (16)));
-+ typedef long long __v2di __attribute__ ((__vector_size__ (16)));
-+
-+ __m128i pclmulqdq_test (__m128i __X, __m128i __Y)
-+ {
-+ return (__m128i) __builtin_ia32_pclmulqdq128 ((__v2di)__X,
-+ (__v2di)__Y,
-+ 1);
-+ }
-+ } "-O2 -mpclmul" ]
-+}
-+
- # Return 1 if sse4a instructions can be compiled.
- proc check_effective_target_sse4a { } {
- return [check_no_compiler_messages sse4a object {
-Index: gcc/testsuite/gcc.target/i386/aesdeclast.c
-===================================================================
---- gcc/testsuite/gcc.target/i386/aesdeclast.c (.../gcc-4_3-branch) (revision 0)
-+++ gcc/testsuite/gcc.target/i386/aesdeclast.c (.../ix86/gcc-4_3-branch) (revision 145364)
-@@ -0,0 +1,69 @@
-+/* { dg-do run } */
-+/* { dg-require-effective-target aes } */
-+/* { dg-options "-O2 -maes" } */
-+
-+#include <wmmintrin.h>
-+#include <string.h>
-+
-+#include "aes-check.h"
-+
-+extern void abort (void);
-+
-+#define NUM 1024
-+
-+static __m128i src1[NUM];
-+static __m128i src2[NUM];
-+static __m128i edst[NUM];
-+
-+static __m128i resdst[NUM];
-+
-+/* Initialize input/output vectors. (Currently, there is only one set of
-+ input/output vectors). */
-+
+
+-/* The function searches for bypass with given IN_INSN_RESERV in given
+- BYPASS_LIST. */
+-static struct bypass_decl *
+-find_bypass (struct bypass_decl *bypass_list,
+- struct insn_reserv_decl *in_insn_reserv)
++/* The function inserts BYPASS in the list of bypasses of the
++ corresponding output insn. The order of bypasses in the list is
++ decribed in a comment for member `bypass_list' (see above). If
++ there is already the same bypass in the list the function reports
++ this and does nothing. */
+static void
-+init_data (__m128i *s1, __m128i *s2, __m128i *d)
-+{
-+ int i;
-+
-+ for (i = 0; i < NUM; i++)
++insert_bypass (struct bypass_decl *bypass)
+ {
+- struct bypass_decl *bypass;
+-
+- for (bypass = bypass_list; bypass != NULL; bypass = bypass->next)
+- if (bypass->in_insn_reserv == in_insn_reserv)
+- break;
+- return bypass;
++ struct bypass_decl *curr, *last;
++ struct insn_reserv_decl *out_insn_reserv = bypass->out_insn_reserv;
++ struct insn_reserv_decl *in_insn_reserv = bypass->in_insn_reserv;
++
++ for (curr = out_insn_reserv->bypass_list, last = NULL;
++ curr != NULL;
++ last = curr, curr = curr->next)
++ if (curr->in_insn_reserv == in_insn_reserv)
++ {
++ if ((bypass->bypass_guard_name != NULL
++ && curr->bypass_guard_name != NULL
++ && ! strcmp (bypass->bypass_guard_name, curr->bypass_guard_name))
++ || bypass->bypass_guard_name == curr->bypass_guard_name)
++ {
++ if (bypass->bypass_guard_name == NULL)
++ {
++ if (!w_flag)
++ error ("the same bypass `%s - %s' is already defined",
++ bypass->out_insn_name, bypass->in_insn_name);
++ else
++ warning (0, "the same bypass `%s - %s' is already defined",
++ bypass->out_insn_name, bypass->in_insn_name);
++ }
++ else if (!w_flag)
++ error ("the same bypass `%s - %s' (guard %s) is already defined",
++ bypass->out_insn_name, bypass->in_insn_name,
++ bypass->bypass_guard_name);
++ else
++ warning
++ (0, "the same bypass `%s - %s' (guard %s) is already defined",
++ bypass->out_insn_name, bypass->in_insn_name,
++ bypass->bypass_guard_name);
++ return;
++ }
++ if (curr->bypass_guard_name == NULL)
++ break;
++ if (curr->next == NULL || curr->next->in_insn_reserv != in_insn_reserv)
++ {
++ last = curr;
++ break;
++ }
++
++ }
++ if (last == NULL)
+ {
-+ s1[i] = _mm_setr_epi32 (0x5d53475d, 0x63746f72,
-+ 0x73745665, 0x7b5b5465);
-+ s2[i] = _mm_setr_epi32 (0x726f6e5d, 0x5b477565,
-+ 0x68617929, 0x48692853);
-+ d[i] = _mm_setr_epi32 (0x72a593d0, 0xd410637b,
-+ 0x6b317f95, 0xc5a391ef);
++ bypass->next = out_insn_reserv->bypass_list;
++ out_insn_reserv->bypass_list = bypass;
+ }
-+}
-+
-+static void
-+aes_test (void)
-+{
-+ int i;
-+
-+ init_data (src1, src2, edst);
-+
-+ for (i = 0; i < NUM; i += 16)
++ else
+ {
-+ resdst[i] = _mm_aesdeclast_si128 (src1[i], src2[i]);
-+ resdst[i + 1] = _mm_aesdeclast_si128 (src1[i + 1], src2[i + 1]);
-+ resdst[i + 2] = _mm_aesdeclast_si128 (src1[i + 2], src2[i + 2]);
-+ resdst[i + 3] = _mm_aesdeclast_si128 (src1[i + 3], src2[i + 3]);
-+ resdst[i + 4] = _mm_aesdeclast_si128 (src1[i + 4], src2[i + 4]);
-+ resdst[i + 5] = _mm_aesdeclast_si128 (src1[i + 5], src2[i + 5]);
-+ resdst[i + 6] = _mm_aesdeclast_si128 (src1[i + 6], src2[i + 6]);
-+ resdst[i + 7] = _mm_aesdeclast_si128 (src1[i + 7], src2[i + 7]);
-+ resdst[i + 8] = _mm_aesdeclast_si128 (src1[i + 8], src2[i + 8]);
-+ resdst[i + 9] = _mm_aesdeclast_si128 (src1[i + 9], src2[i + 9]);
-+ resdst[i + 10] = _mm_aesdeclast_si128 (src1[i + 10], src2[i + 10]);
-+ resdst[i + 11] = _mm_aesdeclast_si128 (src1[i + 11], src2[i + 11]);
-+ resdst[i + 12] = _mm_aesdeclast_si128 (src1[i + 12], src2[i + 12]);
-+ resdst[i + 13] = _mm_aesdeclast_si128 (src1[i + 13], src2[i + 13]);
-+ resdst[i + 14] = _mm_aesdeclast_si128 (src1[i + 14], src2[i + 14]);
-+ resdst[i + 15] = _mm_aesdeclast_si128 (src1[i + 15], src2[i + 15]);
++ bypass->next = last->next;
++ last->next = bypass;
+ }
-+
-+ for (i = 0; i < NUM; i++)
-+ if (memcmp (edst + i, resdst + i, sizeof (__m128i)))
-+ abort ();
-+}
-Index: gcc/testsuite/gcc.target/i386/pclmulqdq.c
+ }
+
+ /* The function processes pipeline description declarations, checks
+@@ -2391,7 +2447,6 @@
+ decl_t decl_in_table;
+ decl_t out_insn_reserv;
+ decl_t in_insn_reserv;
+- struct bypass_decl *bypass;
+ int automaton_presence;
+ int i;
+
+@@ -2514,36 +2569,7 @@
+ = DECL_INSN_RESERV (out_insn_reserv);
+ DECL_BYPASS (decl)->in_insn_reserv
+ = DECL_INSN_RESERV (in_insn_reserv);
+- bypass
+- = find_bypass (DECL_INSN_RESERV (out_insn_reserv)->bypass_list,
+- DECL_BYPASS (decl)->in_insn_reserv);
+- if (bypass != NULL)
+- {
+- if (DECL_BYPASS (decl)->latency == bypass->latency)
+- {
+- if (!w_flag)
+- error
+- ("the same bypass `%s - %s' is already defined",
+- DECL_BYPASS (decl)->out_insn_name,
+- DECL_BYPASS (decl)->in_insn_name);
+- else
+- warning
+- (0, "the same bypass `%s - %s' is already defined",
+- DECL_BYPASS (decl)->out_insn_name,
+- DECL_BYPASS (decl)->in_insn_name);
+- }
+- else
+- error ("bypass `%s - %s' is already defined",
+- DECL_BYPASS (decl)->out_insn_name,
+- DECL_BYPASS (decl)->in_insn_name);
+- }
+- else
+- {
+- DECL_BYPASS (decl)->next
+- = DECL_INSN_RESERV (out_insn_reserv)->bypass_list;
+- DECL_INSN_RESERV (out_insn_reserv)->bypass_list
+- = DECL_BYPASS (decl);
+- }
++ insert_bypass (DECL_BYPASS (decl));
+ }
+ }
+ }
+@@ -8159,19 +8185,32 @@
+ (advance_cycle_insn_decl)->insn_num));
+ fprintf (output_file, " case %d:\n",
+ bypass->in_insn_reserv->insn_num);
+- if (bypass->bypass_guard_name == NULL)
+- fprintf (output_file, " return %d;\n",
+- bypass->latency);
+- else
++ for (;;)
+ {
+- fprintf (output_file,
+- " if (%s (%s, %s))\n",
+- bypass->bypass_guard_name, INSN_PARAMETER_NAME,
+- INSN2_PARAMETER_NAME);
+- fprintf (output_file,
+- " return %d;\n break;\n",
+- bypass->latency);
++ if (bypass->bypass_guard_name == NULL)
++ {
++ gcc_assert (bypass->next == NULL
++ || (bypass->in_insn_reserv
++ != bypass->next->in_insn_reserv));
++ fprintf (output_file, " return %d;\n",
++ bypass->latency);
++ }
++ else
++ {
++ fprintf (output_file,
++ " if (%s (%s, %s))\n",
++ bypass->bypass_guard_name, INSN_PARAMETER_NAME,
++ INSN2_PARAMETER_NAME);
++ fprintf (output_file, " return %d;\n",
++ bypass->latency);
++ }
++ if (bypass->next == NULL
++ || bypass->in_insn_reserv != bypass->next->in_insn_reserv)
++ break;
++ bypass = bypass->next;
+ }
++ if (bypass->bypass_guard_name != NULL)
++ fprintf (output_file, " break;\n");
+ }
+ fputs (" }\n break;\n", output_file);
+ }
+Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-4a.c
===================================================================
---- gcc/testsuite/gcc.target/i386/pclmulqdq.c (.../gcc-4_3-branch) (revision 0)
-+++ gcc/testsuite/gcc.target/i386/pclmulqdq.c (.../ix86/gcc-4_3-branch) (revision 145364)
-@@ -0,0 +1,87 @@
-+/* { dg-do run } */
-+/* { dg-require-effective-target pclmul } */
-+/* { dg-options "-O2 -mpclmul" } */
+--- gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-4a.c (.../tags/gcc_4_4_0_release) (revision 0)
++++ gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-4a.c (.../branches/ix86/gcc-4_4-branch) (revision 146537)
+@@ -0,0 +1,24 @@
++/* Test for cross x86_64<->w64 abi va_list calls. */
++/* { dg-do run { target i?86-*-linux* x86_64-*-linux* } } */
++/* { dg-options "-O2 -mabi=ms -std=gnu99 -fno-builtin" } */
++/* { dg-additional-sources "vaarg-4b.c" } */
++
++extern __SIZE_TYPE__ __attribute__ ((sysv_abi)) strlen (const char *);
++extern int __attribute__ ((sysv_abi)) sprintf (char *,const char *, ...);
++extern void __attribute__ ((sysv_abi)) abort (void);
+
-+#include <wmmintrin.h>
-+#include <string.h>
++extern void do_cpy (char *, ...);
+
-+#include "pclmul-check.h"
++int __attribute__ ((sysv_abi))
++main ()
++{
++ char s[256];
+
-+extern void abort (void);
++ do_cpy (s, "1","2","3","4", "5", "6", "7", "");
+
-+#define NUM 1024
++ if (s[0] != '1' || s[1] !='2' || s[2] != '3' || s[3] != '4'
++ || s[4] != '5' || s[5] != '6' || s[6] != '7' || s[7] != 0)
++ abort ();
+
-+static __m128i s1[NUM];
-+static __m128i s2[NUM];
-+/* We need this array to generate mem form of inst */
-+static __m128i s2m[NUM];
++ return 0;
++}
+Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-4b.c
+===================================================================
+--- gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-4b.c (.../tags/gcc_4_4_0_release) (revision 0)
++++ gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-4b.c (.../branches/ix86/gcc-4_4-branch) (revision 146537)
+@@ -0,0 +1,31 @@
++/* Test for cross x86_64<->w64 abi va_list calls. */
++/* { dg-options "-O2 -mabi=ms -std=gnu99 -fno-builtin" } */
+
-+static __m128i e_00[NUM];
-+static __m128i e_01[NUM];
-+static __m128i e_10[NUM];
-+static __m128i e_11[NUM];
++#include <stdarg.h>
+
-+static __m128i d_00[NUM];
-+static __m128i d_01[NUM];
-+static __m128i d_10[NUM];
-+static __m128i d_11[NUM];
++extern __SIZE_TYPE__ __attribute__ ((sysv_abi)) strlen (const char *);
++extern int __attribute__ ((sysv_abi)) sprintf (char *, const char *, ...);
+
-+/* Initialize input/output vectors. (Currently, there is only one set
-+ of input/output vectors). */
+static void
-+init_data (__m128i *ls1, __m128i *ls2, __m128i *le_00, __m128i *le_01,
-+ __m128i *le_10, __m128i *le_11)
++vdo_cpy (char *s, va_list argp)
+{
-+ int i;
++ __SIZE_TYPE__ len;
++ char *r = s;
++ char *e;
++ *r = 0;
++ for (;;) {
++ e = va_arg (argp, char *);
++ if (*e == 0) break;
++ sprintf (r,"%s", e);
++ r += strlen (r);
++ }
++}
++
++void
++do_cpy (char *s, ...)
++{
++ va_list argp;
++ va_start (argp, s);
++ vdo_cpy (s, argp);
++ va_end (argp);
++}
+Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-5a.c
+===================================================================
+--- gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-5a.c (.../tags/gcc_4_4_0_release) (revision 0)
++++ gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-5a.c (.../branches/ix86/gcc-4_4-branch) (revision 146537)
+@@ -0,0 +1,17 @@
++/* Test for cross x86_64<->w64 abi va_list calls. */
++/* { dg-do run { target i?86-*-linux* x86_64-*-linux* } } */
++/* { dg-options "-O2 -mabi=ms -std=gnu99 -fno-builtin" } */
++/* { dg-additional-sources "vaarg-5b.c" } */
++
++extern void __attribute__ ((sysv_abi)) abort (void);
++extern int fct2 (int, ...);
+
-+ for (i = 0; i < NUM; i++)
-+ {
<<Diff was trimmed, longer than 597 lines>>
---- CVS-web:
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