packages: kernel-desktop/kernel-gpu-drm-mach64.patch (NEW) - DRM suppport f...
hawk
hawk at pld-linux.org
Sat Nov 28 00:03:44 CET 2009
Author: hawk Date: Fri Nov 27 23:03:44 2009 GMT
Module: packages Tag: HEAD
---- Log message:
- DRM suppport for ATI Mach64 cards
---- Files affected:
packages/kernel-desktop:
kernel-gpu-drm-mach64.patch (NONE -> 1.1) (NEW)
---- Diffs:
================================================================
Index: packages/kernel-desktop/kernel-gpu-drm-mach64.patch
diff -u /dev/null packages/kernel-desktop/kernel-gpu-drm-mach64.patch:1.1
--- /dev/null Sat Nov 28 00:03:44 2009
+++ packages/kernel-desktop/kernel-gpu-drm-mach64.patch Sat Nov 28 00:03:39 2009
@@ -0,0 +1,4140 @@
+mach64 driver from git://anongit.freedesktop.org/git/mesa/drm
+head: c99566fb810c9d8cae5e9cd39d1772b55e2f514c
+
+---
+ drivers/gpu/drm/Kconfig | 11
+ drivers/gpu/drm/Makefile | 1
+ drivers/gpu/drm/mach64/Makefile | 8
+ drivers/gpu/drm/Kconfig | 11
+ drivers/gpu/drm/Makefile | 1
+ drivers/gpu/drm/mach64/Makefile | 8
+ drivers/gpu/drm/mach64/mach64_dma.c | 1778 ++++++++++++++++++++++++++++++++++
+ drivers/gpu/drm/mach64/mach64_drm.h | 256 ++++
+ drivers/gpu/drm/mach64/mach64_drv.c | 105 ++
+ drivers/gpu/drm/mach64/mach64_drv.h | 859 ++++++++++++++++
+ drivers/gpu/drm/mach64/mach64_irq.c | 159 +++
+ drivers/gpu/drm/mach64/mach64_state.c | 910 +++++++++++++++++
+ 9 files changed, 4087 insertions(+)
+
+--- a/drivers/gpu/drm/Kconfig
++++ b/drivers/gpu/drm/Kconfig
+@@ -122,3 +122,14 @@ config DRM_SAVAGE
+ help
+ Choose this option if you have a Savage3D/4/SuperSavage/Pro/Twister
+ chipset. If M is selected the module will be called savage.
++
++config DRM_MACH64
++ tristate "ATI Rage Pro (Mach64)"
++ depends on DRM && PCI
++ help
++ Choose this option if you have an ATI Rage Pro (mach64 chipset)
++ graphics card. Example cards include: 3D Rage Pro, Xpert 98,
++ 3D Rage LT Pro, 3D Rage XL/XC, and 3D Rage Mobility (P/M, M1).
++ Cards earlier than ATI Rage Pro (e.g. Rage II) are not supported.
++ If M is selected, the module will be called mach64. AGP support for
++ this card is strongly suggested (unless you have a PCI version).
+--- /dev/null
++++ b/drivers/gpu/drm/mach64/Makefile
+@@ -0,0 +1,8 @@
++#
++# Makefile for the drm device driver. This driver provides support for the
++# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
++
++ccflags-y = -Iinclude/drm
++mach64-y := mach64_drv.o mach64_dma.o mach64_irq.o mach64_state.o
++
++obj-$(CONFIG_DRM_MACH64) += mach64.o
+--- /dev/null
++++ b/drivers/gpu/drm/mach64/mach64_dma.c
+@@ -0,0 +1,1778 @@
++/* mach64_dma.c -- DMA support for mach64 (Rage Pro) driver -*- linux-c -*- */
++/**
++ * \file mach64_dma.c
++ * DMA support for mach64 (Rage Pro) driver
++ *
++ * \author Gareth Hughes <gareth at valinux.com>
++ * \author Frank C. Earl <fearl at airmail.net>
++ * \author Leif Delgass <ldelgass at retinalburn.net>
++ * \author José Fonseca <j_r_fonseca at yahoo.co.uk>
++ */
++
++/*
++ * Copyright 2000 Gareth Hughes
++ * Copyright 2002 Frank C. Earl
++ * Copyright 2002-2003 Leif Delgass
++ * All Rights Reserved.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice (including the next
++ * paragraph) shall be included in all copies or substantial portions of the
++ * Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT OWNER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
++ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#include "drmP.h"
++#include "drm.h"
++#include "mach64_drm.h"
++#include "mach64_drv.h"
++
++/*******************************************************************/
++/** \name Engine, FIFO control */
++/*@{*/
++
++/**
++ * Waits for free entries in the FIFO.
++ *
++ * \note Most writes to Mach64 registers are automatically routed through
++ * command FIFO which is 16 entry deep. Prior to writing to any draw engine
++ * register one has to ensure that enough FIFO entries are available by calling
++ * this function. Failure to do so may cause the engine to lock.
++ *
++ * \param dev_priv pointer to device private data structure.
++ * \param entries number of free entries in the FIFO to wait for.
++ *
++ * \returns zero on success, or -EBUSY if the timeout (specificed by
++ * drm_mach64_private::usec_timeout) occurs.
++ */
++int mach64_do_wait_for_fifo(drm_mach64_private_t *dev_priv, int entries)
++{
++ int slots = 0, i;
++
++ for (i = 0; i < dev_priv->usec_timeout; i++) {
++ slots = (MACH64_READ(MACH64_FIFO_STAT) & MACH64_FIFO_SLOT_MASK);
++ if (slots <= (0x8000 >> entries))
++ return 0;
++ DRM_UDELAY(1);
++ }
++
++ DRM_INFO("failed! slots=%d entries=%d\n", slots, entries);
++ return -EBUSY;
++}
++
++/**
++ * Wait for the draw engine to be idle.
++ */
++int mach64_do_wait_for_idle(drm_mach64_private_t *dev_priv)
++{
++ int i, ret;
++
++ ret = mach64_do_wait_for_fifo(dev_priv, 16);
++ if (ret < 0)
++ return ret;
++
++ for (i = 0; i < dev_priv->usec_timeout; i++) {
++ if (!(MACH64_READ(MACH64_GUI_STAT) & MACH64_GUI_ACTIVE))
++ return 0;
++ DRM_UDELAY(1);
++ }
++
++ DRM_INFO("failed! GUI_STAT=0x%08x\n", MACH64_READ(MACH64_GUI_STAT));
++ mach64_dump_ring_info(dev_priv);
++ return -EBUSY;
++}
++
++/**
++ * Wait for free entries in the ring buffer.
++ *
++ * The Mach64 bus master can be configured to act as a virtual FIFO, using a
++ * circular buffer (commonly referred as "ring buffer" in other drivers) with
++ * pointers to engine commands. This allows the CPU to do other things while
++ * the graphics engine is busy, i.e., DMA mode.
++ *
++ * This function should be called before writing new entries to the ring
++ * buffer.
++ *
++ * \param dev_priv pointer to device private data structure.
++ * \param n number of free entries in the ring buffer to wait for.
++ *
++ * \returns zero on success, or -EBUSY if the timeout (specificed by
++ * drm_mach64_private_t::usec_timeout) occurs.
++ *
++ * \sa mach64_dump_ring_info()
++ */
++int mach64_wait_ring(drm_mach64_private_t *dev_priv, int n)
++{
++ drm_mach64_descriptor_ring_t *ring = &dev_priv->ring;
++ int i;
++
++ for (i = 0; i < dev_priv->usec_timeout; i++) {
++ mach64_update_ring_snapshot(dev_priv);
++ if (ring->space >= n) {
++ if (i > 0)
++ DRM_DEBUG("%d usecs\n", i);
++ return 0;
++ }
++ DRM_UDELAY(1);
++ }
++
++ /* FIXME: This is being ignored... */
++ DRM_ERROR("failed!\n");
++ mach64_dump_ring_info(dev_priv);
++ return -EBUSY;
++}
++
++/**
++ * Wait until all DMA requests have been processed...
++ *
++ * \sa mach64_wait_ring()
++ */
++static int mach64_ring_idle(drm_mach64_private_t *dev_priv)
++{
++ drm_mach64_descriptor_ring_t *ring = &dev_priv->ring;
++ u32 head;
++ int i;
++
++ head = ring->head;
++ i = 0;
++ while (i < dev_priv->usec_timeout) {
++ mach64_update_ring_snapshot(dev_priv);
++ if (ring->head == ring->tail &&
++ !(MACH64_READ(MACH64_GUI_STAT) & MACH64_GUI_ACTIVE)) {
++ if (i > 0)
++ DRM_DEBUG("%d usecs\n", i);
++ return 0;
++ }
++ if (ring->head == head) {
++ ++i;
++ } else {
++ head = ring->head;
++ i = 0;
++ }
++ DRM_UDELAY(1);
++ }
++
++ DRM_INFO("failed! GUI_STAT=0x%08x\n", MACH64_READ(MACH64_GUI_STAT));
++ mach64_dump_ring_info(dev_priv);
++ return -EBUSY;
++}
++
++/**
++ * Reset the the ring buffer descriptors.
++ *
++ * \sa mach64_do_engine_reset()
++ */
++static void mach64_ring_reset(drm_mach64_private_t *dev_priv)
++{
++ drm_mach64_descriptor_ring_t *ring = &dev_priv->ring;
++
++ mach64_do_release_used_buffers(dev_priv);
++ ring->head_addr = ring->start_addr;
++ ring->head = ring->tail = 0;
++ ring->space = ring->size;
++
++ MACH64_WRITE(MACH64_BM_GUI_TABLE_CMD,
++ ring->head_addr | MACH64_CIRCULAR_BUF_SIZE_16KB);
++
++ dev_priv->ring_running = 0;
++}
++
++/**
++ * Ensure the all the queued commands will be processed.
++ */
++int mach64_do_dma_flush(drm_mach64_private_t *dev_priv)
++{
++ /* FIXME: It's not necessary to wait for idle when flushing
++ * we just need to ensure the ring will be completely processed
++ * in finite time without another ioctl
++ */
++ return mach64_ring_idle(dev_priv);
++}
++
++/**
++ * Stop all DMA activity.
++ */
++int mach64_do_dma_idle(drm_mach64_private_t *dev_priv)
++{
++ int ret;
++
++ /* wait for completion */
++ if ((ret = mach64_ring_idle(dev_priv)) < 0) {
++ DRM_ERROR("failed BM_GUI_TABLE=0x%08x tail: %u\n",
++ MACH64_READ(MACH64_BM_GUI_TABLE),
++ dev_priv->ring.tail);
++ return ret;
++ }
++
++ mach64_ring_stop(dev_priv);
++
++ /* clean up after pass */
++ mach64_do_release_used_buffers(dev_priv);
++ return 0;
++}
++
++/**
++ * Reset the engine. This will stop the DMA if it is running.
++ */
++int mach64_do_engine_reset(drm_mach64_private_t *dev_priv)
++{
++ u32 tmp;
++
++ DRM_DEBUG("\n");
++
++ /* Kill off any outstanding DMA transfers.
++ */
++ tmp = MACH64_READ(MACH64_BUS_CNTL);
++ MACH64_WRITE(MACH64_BUS_CNTL, tmp | MACH64_BUS_MASTER_DIS);
++
++ /* Reset the GUI engine (high to low transition).
++ */
++ tmp = MACH64_READ(MACH64_GEN_TEST_CNTL);
++ MACH64_WRITE(MACH64_GEN_TEST_CNTL, tmp & ~MACH64_GUI_ENGINE_ENABLE);
++ /* Enable the GUI engine
++ */
++ tmp = MACH64_READ(MACH64_GEN_TEST_CNTL);
++ MACH64_WRITE(MACH64_GEN_TEST_CNTL, tmp | MACH64_GUI_ENGINE_ENABLE);
++
++ /* ensure engine is not locked up by clearing any FIFO or HOST errors
++ */
++ tmp = MACH64_READ(MACH64_BUS_CNTL);
++ MACH64_WRITE(MACH64_BUS_CNTL, tmp | 0x00a00000);
++
++ /* Once GUI engine is restored, disable bus mastering */
++ MACH64_WRITE(MACH64_SRC_CNTL, 0);
++
++ /* Reset descriptor ring */
++ mach64_ring_reset(dev_priv);
++
++ return 0;
++}
++
++/*@}*/
++
++
++/*******************************************************************/
++/** \name Debugging output */
++/*@{*/
++
++/**
++ * Dump engine registers values.
++ */
++void mach64_dump_engine_info(drm_mach64_private_t *dev_priv)
++{
++ DRM_INFO("\n");
++ if (!dev_priv->is_pci) {
++ DRM_INFO(" AGP_BASE = 0x%08x\n",
++ MACH64_READ(MACH64_AGP_BASE));
++ DRM_INFO(" AGP_CNTL = 0x%08x\n",
++ MACH64_READ(MACH64_AGP_CNTL));
++ }
++ DRM_INFO(" ALPHA_TST_CNTL = 0x%08x\n",
++ MACH64_READ(MACH64_ALPHA_TST_CNTL));
++ DRM_INFO("\n");
++ DRM_INFO(" BM_COMMAND = 0x%08x\n",
++ MACH64_READ(MACH64_BM_COMMAND));
++ DRM_INFO("BM_FRAME_BUF_OFFSET = 0x%08x\n",
++ MACH64_READ(MACH64_BM_FRAME_BUF_OFFSET));
++ DRM_INFO(" BM_GUI_TABLE = 0x%08x\n",
++ MACH64_READ(MACH64_BM_GUI_TABLE));
++ DRM_INFO(" BM_STATUS = 0x%08x\n",
++ MACH64_READ(MACH64_BM_STATUS));
++ DRM_INFO(" BM_SYSTEM_MEM_ADDR = 0x%08x\n",
++ MACH64_READ(MACH64_BM_SYSTEM_MEM_ADDR));
++ DRM_INFO(" BM_SYSTEM_TABLE = 0x%08x\n",
++ MACH64_READ(MACH64_BM_SYSTEM_TABLE));
++ DRM_INFO(" BUS_CNTL = 0x%08x\n",
++ MACH64_READ(MACH64_BUS_CNTL));
++ DRM_INFO("\n");
++ /* DRM_INFO( " CLOCK_CNTL = 0x%08x\n", MACH64_READ( MACH64_CLOCK_CNTL ) ); */
++ DRM_INFO(" CLR_CMP_CLR = 0x%08x\n",
++ MACH64_READ(MACH64_CLR_CMP_CLR));
++ DRM_INFO(" CLR_CMP_CNTL = 0x%08x\n",
++ MACH64_READ(MACH64_CLR_CMP_CNTL));
++ /* DRM_INFO( " CLR_CMP_MSK = 0x%08x\n", MACH64_READ( MACH64_CLR_CMP_MSK ) ); */
++ DRM_INFO(" CONFIG_CHIP_ID = 0x%08x\n",
++ MACH64_READ(MACH64_CONFIG_CHIP_ID));
++ DRM_INFO(" CONFIG_CNTL = 0x%08x\n",
++ MACH64_READ(MACH64_CONFIG_CNTL));
++ DRM_INFO(" CONFIG_STAT0 = 0x%08x\n",
++ MACH64_READ(MACH64_CONFIG_STAT0));
++ DRM_INFO(" CONFIG_STAT1 = 0x%08x\n",
++ MACH64_READ(MACH64_CONFIG_STAT1));
++ DRM_INFO(" CONFIG_STAT2 = 0x%08x\n",
++ MACH64_READ(MACH64_CONFIG_STAT2));
++ DRM_INFO(" CRC_SIG = 0x%08x\n", MACH64_READ(MACH64_CRC_SIG));
++ DRM_INFO(" CUSTOM_MACRO_CNTL = 0x%08x\n",
++ MACH64_READ(MACH64_CUSTOM_MACRO_CNTL));
++ DRM_INFO("\n");
++ /* DRM_INFO( " DAC_CNTL = 0x%08x\n", MACH64_READ( MACH64_DAC_CNTL ) ); */
++ /* DRM_INFO( " DAC_REGS = 0x%08x\n", MACH64_READ( MACH64_DAC_REGS ) ); */
++ DRM_INFO(" DP_BKGD_CLR = 0x%08x\n",
++ MACH64_READ(MACH64_DP_BKGD_CLR));
++ DRM_INFO(" DP_FRGD_CLR = 0x%08x\n",
++ MACH64_READ(MACH64_DP_FRGD_CLR));
++ DRM_INFO(" DP_MIX = 0x%08x\n", MACH64_READ(MACH64_DP_MIX));
++ DRM_INFO(" DP_PIX_WIDTH = 0x%08x\n",
++ MACH64_READ(MACH64_DP_PIX_WIDTH));
++ DRM_INFO(" DP_SRC = 0x%08x\n", MACH64_READ(MACH64_DP_SRC));
++ DRM_INFO(" DP_WRITE_MASK = 0x%08x\n",
++ MACH64_READ(MACH64_DP_WRITE_MASK));
++ DRM_INFO(" DSP_CONFIG = 0x%08x\n",
++ MACH64_READ(MACH64_DSP_CONFIG));
++ DRM_INFO(" DSP_ON_OFF = 0x%08x\n",
++ MACH64_READ(MACH64_DSP_ON_OFF));
++ DRM_INFO(" DST_CNTL = 0x%08x\n",
++ MACH64_READ(MACH64_DST_CNTL));
++ DRM_INFO(" DST_OFF_PITCH = 0x%08x\n",
++ MACH64_READ(MACH64_DST_OFF_PITCH));
++ DRM_INFO("\n");
++ /* DRM_INFO( " EXT_DAC_REGS = 0x%08x\n", MACH64_READ( MACH64_EXT_DAC_REGS ) ); */
++ DRM_INFO(" EXT_MEM_CNTL = 0x%08x\n",
++ MACH64_READ(MACH64_EXT_MEM_CNTL));
++ DRM_INFO("\n");
++ DRM_INFO(" FIFO_STAT = 0x%08x\n",
++ MACH64_READ(MACH64_FIFO_STAT));
++ DRM_INFO("\n");
++ DRM_INFO(" GEN_TEST_CNTL = 0x%08x\n",
++ MACH64_READ(MACH64_GEN_TEST_CNTL));
++ /* DRM_INFO( " GP_IO = 0x%08x\n", MACH64_READ( MACH64_GP_IO ) ); */
++ DRM_INFO(" GUI_CMDFIFO_DATA = 0x%08x\n",
++ MACH64_READ(MACH64_GUI_CMDFIFO_DATA));
++ DRM_INFO(" GUI_CMDFIFO_DEBUG = 0x%08x\n",
++ MACH64_READ(MACH64_GUI_CMDFIFO_DEBUG));
++ DRM_INFO(" GUI_CNTL = 0x%08x\n",
++ MACH64_READ(MACH64_GUI_CNTL));
++ DRM_INFO(" GUI_STAT = 0x%08x\n",
++ MACH64_READ(MACH64_GUI_STAT));
++ DRM_INFO(" GUI_TRAJ_CNTL = 0x%08x\n",
++ MACH64_READ(MACH64_GUI_TRAJ_CNTL));
++ DRM_INFO("\n");
++ DRM_INFO(" HOST_CNTL = 0x%08x\n",
++ MACH64_READ(MACH64_HOST_CNTL));
++ DRM_INFO(" HW_DEBUG = 0x%08x\n",
++ MACH64_READ(MACH64_HW_DEBUG));
++ DRM_INFO("\n");
++ DRM_INFO(" MEM_ADDR_CONFIG = 0x%08x\n",
++ MACH64_READ(MACH64_MEM_ADDR_CONFIG));
++ DRM_INFO(" MEM_BUF_CNTL = 0x%08x\n",
++ MACH64_READ(MACH64_MEM_BUF_CNTL));
++ DRM_INFO("\n");
++ DRM_INFO(" PAT_REG0 = 0x%08x\n",
++ MACH64_READ(MACH64_PAT_REG0));
++ DRM_INFO(" PAT_REG1 = 0x%08x\n",
++ MACH64_READ(MACH64_PAT_REG1));
++ DRM_INFO("\n");
++ DRM_INFO(" SC_LEFT = 0x%08x\n", MACH64_READ(MACH64_SC_LEFT));
++ DRM_INFO(" SC_RIGHT = 0x%08x\n",
++ MACH64_READ(MACH64_SC_RIGHT));
++ DRM_INFO(" SC_TOP = 0x%08x\n", MACH64_READ(MACH64_SC_TOP));
++ DRM_INFO(" SC_BOTTOM = 0x%08x\n",
++ MACH64_READ(MACH64_SC_BOTTOM));
++ DRM_INFO("\n");
++ DRM_INFO(" SCALE_3D_CNTL = 0x%08x\n",
++ MACH64_READ(MACH64_SCALE_3D_CNTL));
++ DRM_INFO(" SCRATCH_REG0 = 0x%08x\n",
++ MACH64_READ(MACH64_SCRATCH_REG0));
++ DRM_INFO(" SCRATCH_REG1 = 0x%08x\n",
++ MACH64_READ(MACH64_SCRATCH_REG1));
++ DRM_INFO(" SETUP_CNTL = 0x%08x\n",
++ MACH64_READ(MACH64_SETUP_CNTL));
++ DRM_INFO(" SRC_CNTL = 0x%08x\n",
++ MACH64_READ(MACH64_SRC_CNTL));
++ DRM_INFO("\n");
++ DRM_INFO(" TEX_CNTL = 0x%08x\n",
++ MACH64_READ(MACH64_TEX_CNTL));
++ DRM_INFO(" TEX_SIZE_PITCH = 0x%08x\n",
++ MACH64_READ(MACH64_TEX_SIZE_PITCH));
++ DRM_INFO(" TIMER_CONFIG = 0x%08x\n",
++ MACH64_READ(MACH64_TIMER_CONFIG));
++ DRM_INFO("\n");
++ DRM_INFO(" Z_CNTL = 0x%08x\n", MACH64_READ(MACH64_Z_CNTL));
++ DRM_INFO(" Z_OFF_PITCH = 0x%08x\n",
++ MACH64_READ(MACH64_Z_OFF_PITCH));
++ DRM_INFO("\n");
++}
++
++#define MACH64_DUMP_CONTEXT 3
++
++/**
++ * Used by mach64_dump_ring_info() to dump the contents of the current buffer
++ * pointed by the ring head.
++ */
++static void mach64_dump_buf_info(drm_mach64_private_t *dev_priv,
++ struct drm_buf *buf)
++{
++ u32 addr = GETBUFADDR(buf);
++ u32 used = buf->used >> 2;
++ u32 sys_addr = MACH64_READ(MACH64_BM_SYSTEM_MEM_ADDR);
++ u32 *p = GETBUFPTR(buf);
++ int skipped = 0;
++
++ DRM_INFO("buffer contents:\n");
++
++ while (used) {
++ u32 reg, count;
++
++ reg = le32_to_cpu(*p++);
++ if (addr <= GETBUFADDR(buf) + MACH64_DUMP_CONTEXT * 4 ||
++ (addr >= sys_addr - MACH64_DUMP_CONTEXT * 4 &&
++ addr <= sys_addr + MACH64_DUMP_CONTEXT * 4) ||
++ addr >=
++ GETBUFADDR(buf) + buf->used - MACH64_DUMP_CONTEXT * 4) {
++ DRM_INFO("%08x: 0x%08x\n", addr, reg);
++ }
++ addr += 4;
++ used--;
++
++ count = (reg >> 16) + 1;
++ reg = reg & 0xffff;
++ reg = MMSELECT(reg);
++ while (count && used) {
++ if (addr <= GETBUFADDR(buf) + MACH64_DUMP_CONTEXT * 4 ||
++ (addr >= sys_addr - MACH64_DUMP_CONTEXT * 4 &&
++ addr <= sys_addr + MACH64_DUMP_CONTEXT * 4) ||
++ addr >=
++ GETBUFADDR(buf) + buf->used -
++ MACH64_DUMP_CONTEXT * 4) {
++ DRM_INFO("%08x: 0x%04x = 0x%08x\n", addr,
++ reg, le32_to_cpu(*p));
++ skipped = 0;
++ } else {
++ if (!skipped) {
++ DRM_INFO(" ...\n");
++ skipped = 1;
++ }
++ }
++ p++;
++ addr += 4;
++ used--;
++
++ reg += 4;
++ count--;
++ }
++ }
++
++ DRM_INFO("\n");
++}
++
++/**
++ * Dump the ring state and contents, including the contents of the buffer being
++ * processed by the graphics engine.
++ */
++void mach64_dump_ring_info(drm_mach64_private_t *dev_priv)
++{
++ drm_mach64_descriptor_ring_t *ring = &dev_priv->ring;
++ int i, skipped;
++
++ DRM_INFO("\n");
++
++ DRM_INFO("ring contents:\n");
++ DRM_INFO(" head_addr: 0x%08x head: %u tail: %u\n\n",
++ ring->head_addr, ring->head, ring->tail);
++
++ skipped = 0;
++ for (i = 0; i < ring->size / sizeof(u32); i += 4) {
++ if (i <= MACH64_DUMP_CONTEXT * 4 ||
++ i >= ring->size / sizeof(u32) - MACH64_DUMP_CONTEXT * 4 ||
++ (i >= ring->tail - MACH64_DUMP_CONTEXT * 4 &&
++ i <= ring->tail + MACH64_DUMP_CONTEXT * 4) ||
++ (i >= ring->head - MACH64_DUMP_CONTEXT * 4 &&
++ i <= ring->head + MACH64_DUMP_CONTEXT * 4)) {
++ DRM_INFO(" 0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x%s%s\n",
++ (u32)(ring->start_addr + i * sizeof(u32)),
++ le32_to_cpu(((u32 *) ring->start)[i + 0]),
++ le32_to_cpu(((u32 *) ring->start)[i + 1]),
++ le32_to_cpu(((u32 *) ring->start)[i + 2]),
++ le32_to_cpu(((u32 *) ring->start)[i + 3]),
++ i == ring->head ? " (head)" : "",
++ i == ring->tail ? " (tail)" : "");
++ skipped = 0;
++ } else {
++ if (!skipped) {
++ DRM_INFO(" ...\n");
++ skipped = 1;
++ }
++ }
++ }
++
++ DRM_INFO("\n");
++
++ if (ring->head >= 0 && ring->head < ring->size / sizeof(u32)) {
++ struct list_head *ptr;
++ u32 addr = le32_to_cpu(((u32 *) ring->start)[ring->head + 1]);
++
++ list_for_each(ptr, &dev_priv->pending) {
++ drm_mach64_freelist_t *entry =
++ list_entry(ptr, drm_mach64_freelist_t, list);
++ struct drm_buf *buf = entry->buf;
++
++ u32 buf_addr = GETBUFADDR(buf);
++
++ if (buf_addr <= addr && addr < buf_addr + buf->used)
++ mach64_dump_buf_info(dev_priv, buf);
++ }
++ }
++
++ DRM_INFO("\n");
++ DRM_INFO(" BM_GUI_TABLE = 0x%08x\n",
++ MACH64_READ(MACH64_BM_GUI_TABLE));
++ DRM_INFO("\n");
++ DRM_INFO("BM_FRAME_BUF_OFFSET = 0x%08x\n",
++ MACH64_READ(MACH64_BM_FRAME_BUF_OFFSET));
++ DRM_INFO(" BM_SYSTEM_MEM_ADDR = 0x%08x\n",
++ MACH64_READ(MACH64_BM_SYSTEM_MEM_ADDR));
++ DRM_INFO(" BM_COMMAND = 0x%08x\n",
++ MACH64_READ(MACH64_BM_COMMAND));
++ DRM_INFO("\n");
++ DRM_INFO(" BM_STATUS = 0x%08x\n",
++ MACH64_READ(MACH64_BM_STATUS));
++ DRM_INFO(" BUS_CNTL = 0x%08x\n",
++ MACH64_READ(MACH64_BUS_CNTL));
<<Diff was trimmed, longer than 597 lines>>
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