[packages/kernel] update arm/arm64 configs and patches for 6.15
atler
atler at pld-linux.org
Tue May 27 01:49:16 CEST 2025
commit 77af67a562960d2345a7b0d4bb571dc1dbd51e14
Author: Jan Palus <atler at pld-linux.org>
Date: Mon May 26 23:52:02 2025 +0200
update arm/arm64 configs and patches for 6.15
kernel-multiarch.config | 17 +
kernel.spec | 2 -
rk3588-vop2-improve-modes-handling.patch | 859 -------------------------------
rpi-sound.patch | 18 +-
4 files changed, 26 insertions(+), 870 deletions(-)
---
diff --git a/kernel.spec b/kernel.spec
index 6ed45751..91840509 100644
--- a/kernel.spec
+++ b/kernel.spec
@@ -178,7 +178,6 @@ Patch8001: kernel-pinebook-pro.patch
Patch8002: atheros-disallow-retrain-nongen1-pcie.patch
Patch8004: ath-regd.patch
Patch8005: rkvdec-hevc.patch
-Patch8006: rk3588-vop2-improve-modes-handling.patch
URL: https://www.kernel.org/
AutoReqProv: no
@@ -578,7 +577,6 @@ cd linux-%{basever}
%patch -P8002 -p1
%patch -P8004 -p1
%patch -P8005 -p1
-%patch -P8006 -p1
%endif
%if %{with rt}
diff --git a/kernel-multiarch.config b/kernel-multiarch.config
index e806a9c8..840c6153 100644
--- a/kernel-multiarch.config
+++ b/kernel-multiarch.config
@@ -1000,6 +1000,7 @@ TCG_ATMEL all=m
TCG_INFINEON all=m
TCG_XEN all=m
TCG_CRB all=m
+TCG_ARM_CRB_FFA arm64=m
TCG_VTPM_PROXY all=m
TCG_FTPM_TEE arm=m arm64=m
#- file drivers/char/tpm/st33zp24/Kconfig goes here
@@ -1136,6 +1137,8 @@ CLK_RK3308 arm64=y
CLK_RK3328 arm64=y
CLK_RK3368 arm64=y
CLK_RK3399 arm64=y
+CLK_RK3528 arm64=y
+CLK_RK3562 arm64=y
CLK_RK3568 arm64=y
CLK_RK3576 arm64=y
CLK_RK3588 arm64=y
@@ -2443,6 +2446,7 @@ DRM_PANEL_OSD_OSD101T2587_53TS all=m
DRM_PANEL_PANASONIC_VVX10F034N00 all=m
DRM_PANEL_RASPBERRYPI_TOUCHSCREEN all=m
DRM_PANEL_RAYDIUM_RM67191 all=m
+DRM_PANEL_RAYDIUM_RM67200 arm=m arm64=m
DRM_PANEL_RAYDIUM_RM68200 all=m
DRM_PANEL_RAYDIUM_RM692E5 all=m
DRM_PANEL_RAYDIUM_RM69380 all=m
@@ -2480,6 +2484,7 @@ DRM_PANEL_SONY_TULIP_TRULY_NT35521 all=m
DRM_PANEL_STARTEK_KD070FHFID015 all=m
DRM_PANEL_EDP all=m
DRM_PANEL_SIMPLE all=m
+DRM_PANEL_SUMMIT arm=m arm64=m
DRM_PANEL_SYNAPTICS_R63353 all=m
DRM_PANEL_TDO_TL070WSH30 all=m
DRM_PANEL_TPO_TD028TTEC1 all=m
@@ -2488,6 +2493,7 @@ DRM_PANEL_TPO_TPG110 all=m
DRM_PANEL_TRULY_NT35597_WQXGA all=m
DRM_PANEL_VISIONOX_R66451 all=m
DRM_PANEL_VISIONOX_RM69299 all=m
+DRM_PANEL_VISIONOX_RM692E5 arm=m arm64=m
DRM_PANEL_VISIONOX_VTDR6130 all=m
DRM_PANEL_WIDECHIPS_WS2401 all=m
DRM_PANEL_XINPENG_XPP055C272 all=m
@@ -4731,6 +4737,7 @@ SERIAL_IPOCTAL all=m
#- *** FILE: drivers/irqchip/Kconfig ***
#-
AL_FIC all=y
+BCM2712_MIP arm=m arm64=m
BRCMSTB_L2_IRQ arm=m arm64=m
LAN966X_OIC all=m
TS4800_IRQ all=m
@@ -5742,6 +5749,12 @@ VIDEO_ROCKCHIP_ISP1 arm64=m
#-
DVB_C8SECTPFE arm=m
+#-
+#- *** FILE: drivers/media/platform/synopsys/hdmirx/Kconfig ***
+#-
+VIDEO_SYNOPSYS_HDMIRX arm64=m
+VIDEO_SYNOPSYS_HDMIRX_LOAD_DEFAULT_EDID arm64=y
+
#-
#- *** FILE: drivers/media/platform/verisilicon/Kconfig ***
#-
@@ -9350,6 +9363,7 @@ PCI_J721E_EP arm=n arm64=n
PCIE_DW all=y
PCIE_DW_DEBUGFS all=n
PCIE_AL arm64=n
+PCIE_AMD_MDB arm64=y
PCI_MESON all=y
PCI_LAYERSCAPE arm=n
PCI_LAYERSCAPE_EP arm=n
@@ -9626,6 +9640,7 @@ PHY_ROCKCHIP_INNO_CSIDPHY arm64=m
PHY_ROCKCHIP_INNO_DSIDPHY arm64=m
PHY_ROCKCHIP_NANENG_COMBO_PHY arm64=m
PHY_ROCKCHIP_PCIE arm64=m
+PHY_ROCKCHIP_SAMSUNG_DCPHY arm64=m
PHY_ROCKCHIP_SAMSUNG_HDPTX arm64=m
PHY_ROCKCHIP_SNPS_PCIE3 arm64=m
PHY_ROCKCHIP_TYPEC arm64=m
@@ -9753,6 +9768,7 @@ PINCTRL_MESON_AXG arm64=m
PINCTRL_MESON_G12A arm64=m
PINCTRL_MESON_A1 arm64=m
PINCTRL_MESON_S4 arm64=m
+PINCTRL_AMLOGIC_A4 arm64=y
PINCTRL_AMLOGIC_C3 arm64=m
PINCTRL_AMLOGIC_T7 arm64=m
@@ -11761,6 +11777,7 @@ SCSI_UFS_DWC_TC_PCI all=m
SCSI_UFSHCD_PLATFORM all=m
SCSI_UFS_CDNS_PLATFORM all=m
SCSI_UFS_DWC_TC_PLATFORM all=m
+SCSI_UFS_ROCKCHIP arm64=m
#-
#- *** FILE: drivers/uio/Kconfig ***
diff --git a/rk3588-vop2-improve-modes-handling.patch b/rk3588-vop2-improve-modes-handling.patch
deleted file mode 100644
index bd87c887..00000000
--- a/rk3588-vop2-improve-modes-handling.patch
+++ /dev/null
@@ -1,859 +0,0 @@
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-From: Cristian Ciocaltea <cristian.ciocaltea at collabora.com>
-Date: Tue, 04 Feb 2025 14:40:07 +0200
-Subject: [PATCH v3 4/5] arm64: dts: rockchip: Enable HDMI0 PHY clk provider
- on RK3588
-MIME-Version: 1.0
-Message-Id: <20250204-vop2-hdmi0-disp-modes-v3-4-d71c6a196e58 at collabora.com>
-References: <20250204-vop2-hdmi0-disp-modes-v3-0-d71c6a196e58 at collabora.com>
-In-Reply-To: <20250204-vop2-hdmi0-disp-modes-v3-0-d71c6a196e58 at collabora.com>
-To: Sandy Huang <hjc at rock-chips.com>,
- =?utf-8?q?Heiko_St=C3=BCbner?= <heiko at sntech.de>,
- Andy Yan <andy.yan at rock-chips.com>,
- Maarten Lankhorst <maarten.lankhorst at linux.intel.com>,
- Maxime Ripard <mripard at kernel.org>, Thomas Zimmermann <tzimmermann at suse.de>,
- David Airlie <airlied at gmail.com>, Simona Vetter <simona at ffwll.ch>,
- Rob Herring <robh at kernel.org>, Krzysztof Kozlowski <krzk+dt at kernel.org>,
- Conor Dooley <conor+dt at kernel.org>
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-Since commit c4b09c562086 ("phy: phy-rockchip-samsung-hdptx: Add clock
-provider support"), the HDMI PHY PLL can be used as an alternative and
-more accurate pixel clock source for VOP2 to improve display modes
-handling on RK3588 SoC.
-
-Add the missing #clock-cells property to allow using the clock provider
-functionality of HDMI0 PHY.
-
-Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea at collabora.com>
----
- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
-index 8cfa30837ce72581d0b513a8274ab0177eb5ae15..c2d1f08e55d4cb4b4d2b6a89f26542fdc99fd604 100644
---- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
-@@ -2812,6 +2812,7 @@ hdptxphy_hdmi0: phy at fed60000 {
- reg = <0x0 0xfed60000 0x0 0x2000>;
- clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>;
- clock-names = "ref", "apb";
-+ #clock-cells = <0>;
- #phy-cells = <0>;
- resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>,
- <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>,
-
---
-2.48.1
-
-
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-From: Cristian Ciocaltea <cristian.ciocaltea at collabora.com>
-Date: Tue, 04 Feb 2025 14:40:08 +0200
-Subject: [PATCH v3 5/5] arm64: dts: rockchip: Add HDMI0 PHY PLL clock
- source to VOP2 on RK3588
-MIME-Version: 1.0
-Message-Id: <20250204-vop2-hdmi0-disp-modes-v3-5-d71c6a196e58 at collabora.com>
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-In-Reply-To: <20250204-vop2-hdmi0-disp-modes-v3-0-d71c6a196e58 at collabora.com>
-To: Sandy Huang <hjc at rock-chips.com>,
- =?utf-8?q?Heiko_St=C3=BCbner?= <heiko at sntech.de>,
- Andy Yan <andy.yan at rock-chips.com>,
- Maarten Lankhorst <maarten.lankhorst at linux.intel.com>,
- Maxime Ripard <mripard at kernel.org>, Thomas Zimmermann <tzimmermann at suse.de>,
- David Airlie <airlied at gmail.com>, Simona Vetter <simona at ffwll.ch>,
- Rob Herring <robh at kernel.org>, Krzysztof Kozlowski <krzk+dt at kernel.org>,
- Conor Dooley <conor+dt at kernel.org>
-Cc: kernel at collabora.com, dri-devel at lists.freedesktop.org,
- devicetree at vger.kernel.org, linux-arm-kernel at lists.infradead.org,
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- FUKAUMI Naoki <naoki at radxa.com>
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-
-VOP2 on RK3588 is able to use the HDMI PHY PLL as an alternative and
-more accurate pixel clock source to improve handling of display modes up
-to 4K at 60Hz on video ports 0, 1 and 2.
-
-For now only HDMI0 output is supported, hence add the related PLL clock.
-
-Tested-by: FUKAUMI Naoki <naoki at radxa.com>
-Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea at collabora.com>
----
- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 6 ++++--
- 1 file changed, 4 insertions(+), 2 deletions(-)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
-index c2d1f08e55d4cb4b4d2b6a89f26542fdc99fd604..13146793188c466faabe6a88e6230ba09f36770c 100644
---- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
-@@ -1261,14 +1261,16 @@ vop: vop at fdd90000 {
- <&cru DCLK_VOP1>,
- <&cru DCLK_VOP2>,
- <&cru DCLK_VOP3>,
-- <&cru PCLK_VOP_ROOT>;
-+ <&cru PCLK_VOP_ROOT>,
-+ <&hdptxphy_hdmi0>;
- clock-names = "aclk",
- "hclk",
- "dclk_vp0",
- "dclk_vp1",
- "dclk_vp2",
- "dclk_vp3",
-- "pclk_vop";
-+ "pclk_vop",
-+ "pll_hdmiphy0";
- iommus = <&vop_mmu>;
- power-domains = <&power RK3588_PD_VOP>;
- rockchip,grf = <&sys_grf>;
-
---
-2.48.1
-
-
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- Tue, 4 Feb 2025 13:40:15 +0100 (CET)
-From: Cristian Ciocaltea <cristian.ciocaltea at collabora.com>
-Date: Tue, 04 Feb 2025 14:40:05 +0200
-Subject: [PATCH v3 2/5] drm/rockchip: vop2: Drop unnecessary if_pixclk_rate
- computation
-MIME-Version: 1.0
-Message-Id: <20250204-vop2-hdmi0-disp-modes-v3-2-d71c6a196e58 at collabora.com>
-References: <20250204-vop2-hdmi0-disp-modes-v3-0-d71c6a196e58 at collabora.com>
-In-Reply-To: <20250204-vop2-hdmi0-disp-modes-v3-0-d71c6a196e58 at collabora.com>
-To: Sandy Huang <hjc at rock-chips.com>,
- =?utf-8?q?Heiko_St=C3=BCbner?= <heiko at sntech.de>,
- Andy Yan <andy.yan at rock-chips.com>,
- Maarten Lankhorst <maarten.lankhorst at linux.intel.com>,
- Maxime Ripard <mripard at kernel.org>, Thomas Zimmermann <tzimmermann at suse.de>,
- David Airlie <airlied at gmail.com>, Simona Vetter <simona at ffwll.ch>,
- Rob Herring <robh at kernel.org>, Krzysztof Kozlowski <krzk+dt at kernel.org>,
- Conor Dooley <conor+dt at kernel.org>
-Cc: kernel at collabora.com, dri-devel at lists.freedesktop.org,
- devicetree at vger.kernel.org, linux-arm-kernel at lists.infradead.org,
- linux-rockchip at lists.infradead.org, linux-kernel at vger.kernel.org
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-Precedence: list
-List-Id: Upstream kernel work for Rockchip platforms <linux-rockchip.lists.infradead.org>
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-
-The if_pixclk_rate variable is not being used outside of the if-block in
-rk3588_calc_cru_cfg(), hence move the superfluous assignment from the
-first branch to the inner comment-block.
-
-Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea at collabora.com>
----
- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
-index 17a98845fd31b5b223b734ae9f72f171230aa7cf..2455d4a55abd6751d54b7c6ecad3dda8a614bd36 100644
---- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
-+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
-@@ -1905,8 +1905,8 @@ static unsigned long rk3588_calc_cru_cfg(struct vop2_video_port *vp, int id,
- K = 2;
- }
-
-- if_pixclk_rate = (dclk_core_rate << 1) / K;
- /*
-+ * if_pixclk_rate = (dclk_core_rate << 1) / K;
- * if_dclk_rate = dclk_core_rate / K;
- * *if_pixclk_div = dclk_rate / if_pixclk_rate;
- * *if_dclk_div = dclk_rate / if_dclk_rate;
-
---
-2.48.1
-
-
-_______________________________________________
-Linux-rockchip mailing list
-Linux-rockchip at lists.infradead.org
-http://lists.infradead.org/mailman/listinfo/linux-rockchip
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-From: Cristian Ciocaltea <cristian.ciocaltea at collabora.com>
-Subject: [PATCH v3 0/5] Improve Rockchip VOP2 display modes handling on
- RK3588 HDMI0
-Date: Tue, 04 Feb 2025 14:40:03 +0200
-Message-Id: <20250204-vop2-hdmi0-disp-modes-v3-0-d71c6a196e58 at collabora.com>
-MIME-Version: 1.0
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-X-Change-ID: 20241116-vop2-hdmi0-disp-modes-b39e3619768f
-To: Sandy Huang <hjc at rock-chips.com>,
- =?utf-8?q?Heiko_St=C3=BCbner?= <heiko at sntech.de>,
- Andy Yan <andy.yan at rock-chips.com>,
- Maarten Lankhorst <maarten.lankhorst at linux.intel.com>,
- Maxime Ripard <mripard at kernel.org>, Thomas Zimmermann <tzimmermann at suse.de>,
- David Airlie <airlied at gmail.com>, Simona Vetter <simona at ffwll.ch>,
- Rob Herring <robh at kernel.org>, Krzysztof Kozlowski <krzk+dt at kernel.org>,
- Conor Dooley <conor+dt at kernel.org>
-Cc: kernel at collabora.com, dri-devel at lists.freedesktop.org,
- devicetree at vger.kernel.org, linux-arm-kernel at lists.infradead.org,
- linux-rockchip at lists.infradead.org, linux-kernel at vger.kernel.org,
- FUKAUMI Naoki <naoki at radxa.com>
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-X-BeenThere: linux-rockchip at lists.infradead.org
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-Precedence: list
-List-Id: Upstream kernel work for Rockchip platforms <linux-rockchip.lists.infradead.org>
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- <mailto:linux-rockchip-request at lists.infradead.org?subject=unsubscribe>
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-
-VOP2 support for RK3588 SoC is currently not capable to handle the full
-range of display modes advertised by the connected screens, e.g. it
-doesn't cope well with non-integer refresh rates like 59.94, 29.97,
-23.98, etc.
-
-There are two HDMI PHYs available on RK3588, each providing a PLL that
-can be used by three out of the four VOP2 video ports as an alternative
-and more accurate pixel clock source. They are able to handle display
-modes up to 4K at 60Hz, anything above that, e.g. the maximum supported
-8K at 60Hz resolution, is supposed to be handled by the system CRU.
-
-There is quite a bit of complexity in downstream driver to handle all
-possible usecases - see [1] for a brief description on how was that
-designed to work.
-
-As for the moment HDMI1 output support [2] is not fully merged upstream,
-the patch series targets HDMI0 only.
-
-Additionally, please note that testing any HDMI 2.0 specific modes, e.g.
-4K at 60Hz, requires high TMDS clock ratio and scrambling capability [3].
-
-Thanks,
-Cristian
-
-[1] https://github.com/radxa/kernel/blob/linux-6.1-stan-rkr4.1/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c#L4742
-[2] https://lore.kernel.org/lkml/20241211-rk3588-hdmi1-v2-0-02cdca22ff68@collabora.com/
-[3] https://gitlab.collabora.com/hardware-enablement/rockchip-3588/linux/-/commits/rk3588-hdmi-bridge-v6.14-rc1
-
-Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea at collabora.com>
----
-Changes in v3:
-- Check the already computed clock instead of mode->crtc_clock in the
- conditional that triggers the switch to HDMI PHY PLL
-- Rebased series onto v6.14-rc1
-- Link to v2: https://lore.kernel.org/r/20241211-vop2-hdmi0-disp-modes-v2-0-471cf5001e45@collabora.com
-
-Changes in v2:
-- Collected Acked-by tag from Rob and Tested-by from Naoki
-- Rebased series onto v6.13-rc1
-- Link to v1: https://lore.kernel.org/r/20241116-vop2-hdmi0-disp-modes-v1-0-2bca51db4898@collabora.com
-
----
-Cristian Ciocaltea (5):
- dt-bindings: display: vop2: Add optional PLL clock properties
- drm/rockchip: vop2: Drop unnecessary if_pixclk_rate computation
- drm/rockchip: vop2: Improve display modes handling on RK3588 HDMI0
- arm64: dts: rockchip: Enable HDMI0 PHY clk provider on RK3588
- arm64: dts: rockchip: Add HDMI0 PHY PLL clock source to VOP2 on RK3588
-
- .../bindings/display/rockchip/rockchip-vop2.yaml | 4 +++
- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 7 +++--
- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 36 +++++++++++++++++++++-
- 3 files changed, 44 insertions(+), 3 deletions(-)
----
-base-commit: 2014c95afecee3e76ca4a56956a936e23283f05b
-change-id: 20241116-vop2-hdmi0-disp-modes-b39e3619768f
-
-
-_______________________________________________
-Linux-rockchip mailing list
-Linux-rockchip at lists.infradead.org
-http://lists.infradead.org/mailman/listinfo/linux-rockchip
-
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-From: Cristian Ciocaltea <cristian.ciocaltea at collabora.com>
-Date: Tue, 04 Feb 2025 14:40:04 +0200
-Subject: [PATCH v3 1/5] dt-bindings: display: vop2: Add optional PLL clock
- properties
-MIME-Version: 1.0
-Message-Id: <20250204-vop2-hdmi0-disp-modes-v3-1-d71c6a196e58 at collabora.com>
-References: <20250204-vop2-hdmi0-disp-modes-v3-0-d71c6a196e58 at collabora.com>
-In-Reply-To: <20250204-vop2-hdmi0-disp-modes-v3-0-d71c6a196e58 at collabora.com>
-To: Sandy Huang <hjc at rock-chips.com>,
- =?utf-8?q?Heiko_St=C3=BCbner?= <heiko at sntech.de>,
- Andy Yan <andy.yan at rock-chips.com>,
- Maarten Lankhorst <maarten.lankhorst at linux.intel.com>,
- Maxime Ripard <mripard at kernel.org>, Thomas Zimmermann <tzimmermann at suse.de>,
- David Airlie <airlied at gmail.com>, Simona Vetter <simona at ffwll.ch>,
- Rob Herring <robh at kernel.org>, Krzysztof Kozlowski <krzk+dt at kernel.org>,
- Conor Dooley <conor+dt at kernel.org>
-Cc: kernel at collabora.com, dri-devel at lists.freedesktop.org,
- devicetree at vger.kernel.org, linux-arm-kernel at lists.infradead.org,
- linux-rockchip at lists.infradead.org, linux-kernel at vger.kernel.org
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-
-On RK3588, HDMI PHY PLL can be used as an alternative and more accurate
-pixel clock source for VOP2 video ports 0, 1 and 2.
-
-Document the optional PLL clock properties corresponding to the two HDMI
-PHYs available on the SoC.
-
-Acked-by: Rob Herring (Arm) <robh at kernel.org>
-Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea at collabora.com>
----
- Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml | 4 ++++
- 1 file changed, 4 insertions(+)
-
-diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml
-index 2531726af306bd388c00c3c0a1785b2c7367e2bd..46d956e63338e196361483a668fbf5597ebce24f 100644
---- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml
-+++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml
-@@ -53,6 +53,8 @@ properties:
- - description: Pixel clock for video port 2.
- - description: Pixel clock for video port 3.
- - description: Peripheral(vop grf/dsi) clock.
-+ - description: Alternative pixel clock provided by HDMI0 PHY PLL.
-+ - description: Alternative pixel clock provided by HDMI1 PHY PLL.
-
- clock-names:
- minItems: 5
-@@ -64,6 +66,8 @@ properties:
- - const: dclk_vp2
- - const: dclk_vp3
- - const: pclk_vop
-+ - const: pll_hdmiphy0
-+ - const: pll_hdmiphy1
-
- rockchip,grf:
- $ref: /schemas/types.yaml#/definitions/phandle
-
---
-2.48.1
-
-
-_______________________________________________
-Linux-rockchip mailing list
-Linux-rockchip at lists.infradead.org
-http://lists.infradead.org/mailman/listinfo/linux-rockchip
-
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-From: Cristian Ciocaltea <cristian.ciocaltea at collabora.com>
-Date: Tue, 04 Feb 2025 14:40:06 +0200
-Subject: [PATCH v3 3/5] drm/rockchip: vop2: Improve display modes handling
- on RK3588 HDMI0
-MIME-Version: 1.0
-Message-Id: <20250204-vop2-hdmi0-disp-modes-v3-3-d71c6a196e58 at collabora.com>
-References: <20250204-vop2-hdmi0-disp-modes-v3-0-d71c6a196e58 at collabora.com>
-In-Reply-To: <20250204-vop2-hdmi0-disp-modes-v3-0-d71c6a196e58 at collabora.com>
-To: Sandy Huang <hjc at rock-chips.com>,
- =?utf-8?q?Heiko_St=C3=BCbner?= <heiko at sntech.de>,
- Andy Yan <andy.yan at rock-chips.com>,
- Maarten Lankhorst <maarten.lankhorst at linux.intel.com>,
- Maxime Ripard <mripard at kernel.org>, Thomas Zimmermann <tzimmermann at suse.de>,
- David Airlie <airlied at gmail.com>, Simona Vetter <simona at ffwll.ch>,
- Rob Herring <robh at kernel.org>, Krzysztof Kozlowski <krzk+dt at kernel.org>,
- Conor Dooley <conor+dt at kernel.org>
-Cc: kernel at collabora.com, dri-devel at lists.freedesktop.org,
- devicetree at vger.kernel.org, linux-arm-kernel at lists.infradead.org,
- linux-rockchip at lists.infradead.org, linux-kernel at vger.kernel.org,
- FUKAUMI Naoki <naoki at radxa.com>
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-List-Id: Upstream kernel work for Rockchip platforms <linux-rockchip.lists.infradead.org>
-List-Unsubscribe: <http://lists.infradead.org/mailman/options/linux-rockchip>,
- <mailto:linux-rockchip-request at lists.infradead.org?subject=unsubscribe>
-List-Archive: <http://lists.infradead.org/pipermail/linux-rockchip/>
-List-Post: <mailto:linux-rockchip at lists.infradead.org>
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-List-Subscribe: <http://lists.infradead.org/mailman/listinfo/linux-rockchip>,
- <mailto:linux-rockchip-request at lists.infradead.org?subject=subscribe>
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-Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org at lists.infradead.org
-
-The RK3588 specific implementation is currently quite limited in terms
-of handling the full range of display modes supported by the connected
-screens, e.g. 2560x1440 at 75Hz, 2048x1152 at 60Hz, 1024x768 at 60Hz are just a
-few of them.
-
-Additionally, it doesn't cope well with non-integer refresh rates like
-59.94, 29.97, 23.98, etc.
-
-Make use of HDMI0 PHY PLL as a more accurate DCLK source to handle
-all display modes up to 4K at 60Hz.
-
-Tested-by: FUKAUMI Naoki <naoki at radxa.com>
-Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea at collabora.com>
----
- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 34 ++++++++++++++++++++++++++++
- 1 file changed, 34 insertions(+)
-
-diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
-index 2455d4a55abd6751d54b7c6ecad3dda8a614bd36..afc946ead87091373605e59dbca281a9e91bea57 100644
---- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
-+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
-@@ -159,6 +159,7 @@ struct vop2_video_port {
- struct drm_crtc crtc;
- struct vop2 *vop2;
- struct clk *dclk;
-+ struct clk *dclk_src;
- unsigned int id;
- const struct vop2_video_port_data *data;
-
-@@ -214,6 +215,7 @@ struct vop2 {
- struct clk *hclk;
- struct clk *aclk;
- struct clk *pclk;
-+ struct clk *pll_hdmiphy0;
-
- /* optional internal rgb encoder */
- struct rockchip_rgb *rgb;
-@@ -222,6 +224,8 @@ struct vop2 {
- struct vop2_win win[];
- };
-
-+#define VOP2_MAX_DCLK_RATE 600000000
-+
- #define vop2_output_if_is_hdmi(x) ((x) == ROCKCHIP_VOP2_EP_HDMI0 || \
- (x) == ROCKCHIP_VOP2_EP_HDMI1)
-
-@@ -1155,6 +1159,9 @@ static void vop2_crtc_atomic_disable(struct drm_crtc *crtc,
-
- vop2_crtc_disable_irq(vp, VP_INT_DSP_HOLD_VALID);
-
-+ if (vp->dclk_src)
-+ clk_set_parent(vp->dclk, vp->dclk_src);
-+
- clk_disable_unprepare(vp->dclk);
-
- vop2->enable_count--;
-@@ -2259,6 +2266,27 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc,
-
- vop2_vp_write(vp, RK3568_VP_MIPI_CTRL, 0);
-
-+ /*
-+ * Switch to HDMI PHY PLL as DCLK source for display modes up
-+ * to 4K at 60Hz, if available, otherwise keep using the system CRU.
-+ */
-+ if (vop2->pll_hdmiphy0 && clock <= VOP2_MAX_DCLK_RATE) {
-+ drm_for_each_encoder_mask(encoder, crtc->dev, crtc_state->encoder_mask) {
-+ struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
-+
-+ if (rkencoder->crtc_endpoint_id == ROCKCHIP_VOP2_EP_HDMI0) {
-+ if (!vp->dclk_src)
-+ vp->dclk_src = clk_get_parent(vp->dclk);
-+
-+ ret = clk_set_parent(vp->dclk, vop2->pll_hdmiphy0);
-+ if (ret < 0)
-+ drm_warn(vop2->drm,
-+ "Could not switch to HDMI0 PHY PLL: %d\n", ret);
-+ break;
-+ }
-+ }
-+ }
-+
- clk_set_rate(vp->dclk, clock);
-
- vop2_post_config(crtc);
-@@ -3699,6 +3727,12 @@ static int vop2_bind(struct device *dev, struct device *master, void *data)
- return PTR_ERR(vop2->pclk);
- }
-
-+ vop2->pll_hdmiphy0 = devm_clk_get_optional(vop2->dev, "pll_hdmiphy0");
-+ if (IS_ERR(vop2->pll_hdmiphy0)) {
-+ drm_err(vop2->drm, "failed to get pll_hdmiphy0\n");
-+ return PTR_ERR(vop2->pll_hdmiphy0);
-+ }
-+
- vop2->irq = platform_get_irq(pdev, 0);
- if (vop2->irq < 0) {
- drm_err(vop2->drm, "cannot find irq for vop2\n");
-
---
-2.48.1
-
-
-_______________________________________________
-Linux-rockchip mailing list
-Linux-rockchip at lists.infradead.org
-http://lists.infradead.org/mailman/listinfo/linux-rockchip
-
diff --git a/rpi-sound.patch b/rpi-sound.patch
index ec64337c..7b193b1d 100644
--- a/rpi-sound.patch
+++ b/rpi-sound.patch
@@ -374,7 +374,7 @@
+ if (!dai->dai_fmt)
+ dai->dai_fmt = SND_SOC_DAIFMT_I2S |
+ SND_SOC_DAIFMT_NB_NF |
-+ SND_SOC_DAIFMT_CBM_CFM;
++ SND_SOC_DAIFMT_CBP_CFP;
+
+ snd_rpi_wm8804.dai_link = dai;
+ i2s_node = of_parse_phandle(pdev->dev.of_node,
@@ -636,7 +636,7 @@
+ .init = adau1977_init,
+ .dai_fmt = SND_SOC_DAIFMT_I2S |
+ SND_SOC_DAIFMT_NB_NF |
-+ SND_SOC_DAIFMT_CBM_CFM,
++ SND_SOC_DAIFMT_CBP_CFP,
+ SND_SOC_DAILINK_REG(adau1977),
+ },
+};
@@ -656,7 +656,7 @@
+ .name = "Google voiceHAT SoundCard",
+ .stream_name = "Google voiceHAT SoundCard HiFi",
+ .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
-+ SND_SOC_DAIFMT_CBS_CFS,
++ SND_SOC_DAIFMT_CBC_CFC,
+ SND_SOC_DAILINK_REG(gvchat),
+},
+};
@@ -677,7 +677,7 @@
+ .stream_name = "Hifiberry DAC+DSP SoundCard HiFi",
+ .dai_fmt = SND_SOC_DAIFMT_I2S |
+ SND_SOC_DAIFMT_NB_NF |
-+ SND_SOC_DAIFMT_CBS_CFS,
++ SND_SOC_DAIFMT_CBC_CFC,
+ SND_SOC_DAILINK_REG(hifiberry_dacplusdsp),
+},
+};
@@ -698,7 +698,7 @@
+ .stream_name = "HifiBerry AMP HiFi",
+ .dai_fmt = SND_SOC_DAIFMT_I2S |
+ SND_SOC_DAIFMT_NB_NF |
-+ SND_SOC_DAIFMT_CBS_CFS,
++ SND_SOC_DAIFMT_CBC_CFC,
+ SND_SOC_DAILINK_REG(hifiberry_amp),
+ },
+};
@@ -720,7 +720,7 @@
+ .stream_name = "HifiBerry DAC HiFi",
+ .dai_fmt = SND_SOC_DAIFMT_I2S |
+ SND_SOC_DAIFMT_NB_NF |
-+ SND_SOC_DAIFMT_CBS_CFS,
++ SND_SOC_DAIFMT_CBC_CFC,
+ SND_SOC_DAILINK_REG(hifiberry_dac),
+ },
+};
@@ -740,7 +740,7 @@
+ .name = "RPi-DAC",
+ .stream_name = "RPi-DAC HiFi",
+ .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
-+ SND_SOC_DAIFMT_CBS_CFS,
++ SND_SOC_DAIFMT_CBC_CFC,
+ SND_SOC_DAILINK_REG(rpi_dac),
+},
+};
@@ -762,7 +762,7 @@
+ .stream_name = "Merus Audio Amp",
+ .dai_fmt = SND_SOC_DAIFMT_I2S |
+ SND_SOC_DAIFMT_NB_NF |
-+ SND_SOC_DAIFMT_CBS_CFS,
++ SND_SOC_DAIFMT_CBC_CFC,
+ SND_SOC_DAILINK_REG(merus_amp),
+ },
+};
@@ -785,7 +785,7 @@
+ .init = pifi_mini_210_init,
+ .dai_fmt = SND_SOC_DAIFMT_I2S |
+ SND_SOC_DAIFMT_NB_NF |
-+ SND_SOC_DAIFMT_CBS_CFS,
++ SND_SOC_DAIFMT_CBC_CFC,
+ SND_SOC_DAILINK_REG(pifi_mini_210),
+ },
+};
================================================================
---- gitweb:
http://git.pld-linux.org/gitweb.cgi/packages/kernel.git/commitdiff/77af67a562960d2345a7b0d4bb571dc1dbd51e14
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