Pentium3 w RPM

[undefine@aramin.net]

On Sat, Feb 28, 2004 at 09:01:47AM +0100, Paweł Sakowski wrote:
> > czyli zwykly athlon nie ma.
> 
> A podpada pod PentiumIII? (/usr/sbin/cpuid)

#v+
 eax in    eax      ebx      ecx      edx
00000000 00000001 68747541 444d4163 69746e65
00000001 00000621 00000000 00000000 0183fbff
80000000 80000006 68747541 444d4163 69746e65
80000001 00000721 00000000 00000000 c1c3fbff
80000002 20444d41 6c687441 74286e6f 5020296d
80000003 65636f72 726f7373 00000000 00000000
80000004 00000000 00000000 00000000 00000000
80000005 0408ff08 ff18ff10 40020140 40020140
80000006 00000000 41004100 02002140 00000000

Vendor ID: "AuthenticAMD"; CPUID level 1

AMD-specific functions
Version 00000621:
Family: 6 Model: 2 [Athlon model 2]

Standard feature flags 0183fbff:
Floating Point Unit
Virtual Mode Extensions
Debugging Extensions
Page Size Extensions
Time Stamp Counter (with RDTSC and CR4 disable bit)
Model Specific Registers with RDMSR & WRMSR
PAE - Page Address Extensions
Machine Check Exception
COMPXCHG8B Instruction
APIC
SYSCALL/SYSRET or SYSENTER/SYSEXIT instructions
MTRR - Memory Type Range Registers
Global paging extension
Machine Check Architecture
Conditional Move Instruction
PAT - Page Attribute Table
PSE-36 - Page Size Extensions
MMX instructions
FXSAVE/FXRSTOR
Generation: 7 Model: 2
Extended feature flags c1c3fbff:
Floating Point Unit
Virtual Mode Extensions
Debugging Extensions
Page Size Extensions
Time Stamp Counter (with RDTSC and CR4 disable bit)
Model Specific Registers with RDMSR & WRMSR
PAE - Page Address Extensions
Machine Check Exception
COMPXCHG8B Instruction
APIC
SYSCALL/SYSRET or SYSENTER/SYSEXIT instructions
MTRR - Memory Type Range Registers
Global paging extension
Machine Check Architecture
Conditional Move Instruction
PAT - Page Attribute Table
PSE-36 - Page Size Extensions
AMD MMX Instruction Extensions
MMX instructions
FXSAVE/FXRSTOR
3DNow! Instruction Extensions
3DNow instructions

Processor name string: AMD Athlon(tm) Processor
L1 Cache Information:
2/4-MB Pages:
   Data TLB: associativity 4-way #entries 8
   Instruction TLB: associativity 255-way #entries 8
4-KB Pages:
   Data TLB: associativity 255-way #entries 24
   Instruction TLB: associativity 255-way #entries 16
L1 Data cache:
   size 64 KB associativity 2-way lines per tag 1 line size 64
L1 Instruction cache:
   size 64 KB associativity 2-way lines per tag 1 line size 64

L2 Cache Information:
2/4-MB Pages:
   Data TLB: associativity L2 off #entries 0
   Instruction TLB: associativity L2 off #entries 0
4-KB Pages:
   Data TLB: associativity Direct mapped #entries 0
   Instruction TLB: associativity Direct mapped #entries 0
   size 2 KB associativity L2 off lines per tag 33 line size 64
#v-
czyli raczej nie.

-- 
Andrzej Dopierała
Prywatnie.