arch - centrino?

[pbern@pbern.biz]

On Thu, 3 Jun 2004, Pawe? Sikora wrote:

> > Czy ktos z grupowiczow jest moze rozeznany co to jest za platforma..
> > pentium4 czy pentium3?
> 
> zapodaj nam wynik # x86info
w zalaczniku wynik...

gdybys doradzil czy da sie wyluskac z tego instrukcje i tworzyc pakiety 
specjanie dla senstrino chetnie bym sprobowal postawic builder na ten cel.

Pozdrawiam
Pawel Bernadowski
GG 3377, email kontakt w pbern.biz
-------------- następna część ---------
x86info v1.11.  Dave Jones 2001, 2002
Feedback to <davej w suse.de>.

Found 1 CPU
eax in: 0x00000000, eax = 00000002 ebx = 756e6547 ecx = 6c65746e edx = 49656e69
eax in: 0x00000001, eax = 00000695 ebx = 00000816 ecx = 00000180 edx = a7e9fbbf
eax in: 0x00000002, eax = 02b3b001 ebx = 00000000 ecx = 00000000 edx = 2c043040

eax in: 0x80000000, eax = 80000004 ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x80000001, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x80000002, eax = 20202020 ebx = 20202020 ecx = 65746e49 edx = 2952286c
eax in: 0x80000003, eax = 6e655020 ebx = 6d756974 ecx = 20295228 edx = 7270204d
eax in: 0x80000004, eax = 7365636f ebx = 20726f73 ecx = 30303431 edx = 007a484d

Family: 6 Model: 9 Stepping: 5 Type: 0
CPU Model: Unknown CPU Original OEM
Feature flags:
	Onboard FPU
	Virtual Mode Extensions
	Debugging Extensions
	Page Size Extensions
	Time Stamp Counter
	Model-Specific Registers
	Machine Check Architecture
	CMPXCHG8 instruction
	Onboard APIC
	SYSENTER/SYSEXIT
	Memory Type Range Registers
	Page Global Enable
	Machine Check Architecture
	CMOV instruction
	Page Attribute Table
	CLFLUSH instruction
	Debug Trace Store
	ACPI via MSR
	MMX support
	FXSAVE and FXRESTORE instructions
	SSE support
	SSE2 support
	Automatic clock Control
	Pending Break Enable


unknown TLB/cache descriptor:
	0xb0
unknown TLB/cache descriptor:
	0xb3
Instruction TLB: 4MB pages, fully associative, 2 entries
No L2 cache
unknown TLB/cache descriptor:
	0x30
Data TLB: 4MB pages, 4-way associative, 8 entries
unknown TLB/cache descriptor:
	0x2c


MTRR registers:
MTRRcap (0xfe): MTRRphysBase0 (0x200): MTRRphysMask0 (0x201): MTRRphysBase1 (0x202): MTRRphysMask1 (0x203): MTRRphysBase2 (0x204): MTRRphysMask2 (0x205): MTRRphysBase3 (0x206): MTRRphysMask3 (0x207): MTRRphysBase4 (0x208): MTRRphysMask4 (0x209): MTRRphysBase5 (0x20a): MTRRphysMask5 (0x20b): MTRRphysBase6 (0x20c): MTRRphysMask6 (0x20d): MTRRphysBase7 (0x20e): MTRRphysMask7 (0x20f): MTRRfix64K_00000 (0x250): MTRRfix16K_80000 (0x258): MTRRfix16K_A0000 (0x259): MTRRfix4K_C8000 (0x269): MTRRfix4K_D0000 0x26a: MTRRfix4K_D8000 0x26b: MTRRfix4K_E0000 0x26c: MTRRfix4K_E8000 0x26d: MTRRfix4K_F0000 0x26e: MTRRfix4K_F8000 0x26f: MTRRdefType (0x2ff): 

1399.87 MHz processor (estimate).