Prośba o testy (SVGATextMode + karty nVidii)
Przemysław Białek
lobo w chello.pl
Wto, 25 Maj 2004, 21:07:56 CEST
Witam!
Napisałem patcha na SVGATextmode, który rozszerza funckjonalność tego
programu na wiekszość kart nVidii. Wyciągnąłem kod z OpenSource'owego
sterownika nVidii w XFree86/X11R6.7.0 i dzięki zmianom powinny ruszyć
wszystke karty serii FX5600 i FX5700. Nie powinien on zmieniać
zachowania na kartach dotychczas obsługiwanych. Z tego co widziałem
w sterownikach X'owych wszystkie karty nVidii których pci_id dodaję
powinny być dobrze obsługiwane, przynajmniej nie widzę róznic w tej
części kodu która dotyczy zmiany pixel clock. Niestety w tej chwili
mam dostep tylko do FX 5600, więc prosiłbym o przetestowanie tego kodu
i ewentualne wrzucenie do cvs'u.
Patch na stm został połączony z patchem SVGATextmode-Geforce.patch, ale
zmieniłem mu nazwę, gdyż dotyczy on nie tylko GF, lecz ogólnie kart
nVidii. W załącznikach patch na speca, oraz dodatkowo rozszerzony patch
na llh (zmiany dotyczące includowania <asm/io.h>).
Patche już były raz przesyłane, ale jakoś przeszły bez echa. Mam
nadzieję, że teraz lepiej opisałem zmiany jakie zrobiłem, poprawiłem
również samego patcha więc myślę, że jest szansa na dodanie tego.
--
Pozdrawiam
Przemysław Białek
-------------- następna część ---------
--- SVGATextMode.spec.orig 2004-05-25 18:43:20.038645408 +0200
+++ SVGATextMode.spec 2004-05-25 19:07:17.041187816 +0200
@@ -7,7 +7,7 @@
Summary(uk): őÔÉĚŚÔÁ ÄĚŃ ĐĎËŇÁÝĹÎÎŃ ÚĎ×ÎŚŰÎŘĎÇĎ ×ÉÇĚŃÄŐ ÔĹËÓÔĎ×ÉČ ËĎÎÓĎĚĹĘ
Name: SVGATextMode
Version: 1.10
-Release: 17
+Release: 18
License: GPL
Group: Applications/System
Source0: ftp://sunsite.unc.edu/pub/Linux/utils/console/%{name}-%{version}-src.tar.gz
@@ -19,7 +19,7 @@
Patch4: %{name}-set80.patch
Patch5: %{name}-Makefile-gcc.patch
Patch6: %{name}-cfgfile.y.patch
-Patch7: %{name}-GeForce.patch
+Patch7: %{name}-Nvidia.patch
Patch8: %{name}-voodoo.patch
Patch9: %{name}-alpha.patch
Patch10: %{name}-gcc33.patch
-------------- następna część ---------
diff -ru SVGATextMode-1.10.orig/SVGATextMode.c SVGATextMode-1.10/SVGATextMode.c
--- SVGATextMode-1.10.orig/SVGATextMode.c 2000-09-03 01:27:19.000000000 +0200
+++ SVGATextMode-1.10/SVGATextMode.c 2004-05-25 18:50:33.888690176 +0200
@@ -35,7 +35,7 @@
#include <fcntl.h>
#ifndef DOS
-# include "fs.h"
+# include <linux/fs.h>
# include <sys/ioctl.h>
# include <sys/kd.h>
# include <ctype.h>
diff -ru SVGATextMode-1.10.orig/vga_prg.h SVGATextMode-1.10/vga_prg.h
--- SVGATextMode-1.10.orig/vga_prg.h 2000-09-03 00:03:07.000000000 +0200
+++ SVGATextMode-1.10/vga_prg.h 2004-05-25 18:55:36.558677344 +0200
@@ -40,14 +40,10 @@
# define ioperm(x,y,z) (0)
# define iopl(x) (0)
#else
-extern int iopl(int);
-# include <asm/io.h>
-# ifdef __ALPHA_IO_H
-# define _ASM_IO_H
-# endif
+# include <sys/io.h>
#endif
-#ifndef _ASM_IO_H
+#ifndef _SYS_IO_H
# ifdef DJGPP
# include <pc.h>
# define outb(data,port) outportb(port,data)
-------------- następna część ---------
diff -ru SVGATextMode-1.10.orig/XFREE/riva128_clock.c SVGATextMode-1.10/XFREE/riva128_clock.c
--- SVGATextMode-1.10.orig/XFREE/riva128_clock.c 2000-07-18 04:47:15.000000000 +0200
+++ SVGATextMode-1.10/XFREE/riva128_clock.c 2004-05-25 20:45:25.594991568 +0200
@@ -80,9 +80,96 @@
#define PCI_DEVICE_ID_NVIDIA_TNT 0x0020
#define PCI_DEVICE_ID_NVIDIA_TNT2 0x0028
#define PCI_DEVICE_ID_NVIDIA_UTNT2 0x0029
+#define PCI_DEVICE_ID_NVIDIA_UNKNOWN_TNT2 0x002A
#define PCI_DEVICE_ID_NVIDIA_VTNT2 0x002C
#define PCI_DEVICE_ID_NVIDIA_UVTNT2 0x002D
#define PCI_DEVICE_ID_NVIDIA_ITNT2 0x00A0
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR 0x0100
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR 0x0101
+#define PCI_DEVICE_ID_NVIDIA_QUADRO 0x0103
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX400 0x0110
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX200 0x0111
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO 0x0112
+#define PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR 0x0113
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS 0x0150
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2 0x0151
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA 0x0152
+#define PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO 0x0153
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460 0x0170
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440 0x0171
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420 0x0172
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX440SE 0x0173
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO 0x0174
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO 0x0175
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO32 0x0176
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_460GO 0x0177
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL 0x0178
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_460_GO64 0x0179
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_200 0x017A
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL 0x017B
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL 0x017C
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_410_GO16 0x017D
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX440_AGP8x 0x0181
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX440SE_AGP8x 0x0182
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX420_AGP8x 0x0183
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_448_GO 0x0186
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_488_GO 0x0187
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_580_XGL 0x0188
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_280_NVS 0x018A
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_380_XGL 0x018B
+#define PCI_DEVICE_ID_NVIDIA_IGEFORCE2 0x01a0
+#define PCI_DEVICE_ID_NVIDIA_IGEFORCE4_MX 0x01F0
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE3 0x0200
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE3_TI200 0x0201
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE3_TI500 0x0202
+#define PCI_DEVICE_ID_NVIDIA_QUADRO_DCC 0x0203
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI4600 0x0250
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI4400 0x0251
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI4200 0x0253
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL 0x0258
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL 0x0259
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL 0x025B
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI4800 0x0280
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI4200_AGP8x 0x0281
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI4800SE 0x0282
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_4200GO 0x0286
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_700GOGL 0x028C
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_980XGL 0x0288
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_780XGL 0x0289
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5800U 0x0301
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5800 0x0302
+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_2000 0x0308
+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1000 0x0309
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600U 0x0311
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600 0x0312
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600SE 0x0314
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5600 0x031A
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5650 0x031B
+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO700 0x031C
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200 0x0320
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200U 0x0321
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200_U 0x0322
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200SE 0x0323
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5200 0x0324
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5250 0x0325
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5200_32M_64M 0x0328
+#define PCI_DEVICE_ID_NVIDIA_QUADRO_NVS_280_PCI 0x032A
+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_500 0x032B
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5300 0x032C
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5100 0x032D
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900U 0x0330
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900 0x0331
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900XT 0x0332
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5950U 0x0333
+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_3000 0x0338
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700U 0x0341
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700 0x0342
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700LE 0x0343
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700VE 0x0344
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700 0x0347
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700_ 0x0348
+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO1000 0x034C
+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1100 0x034E
vgaPCIInformation *vgaPCIInfo;
@@ -92,14 +179,16 @@
#define PRAMDAC_PLL_COEFF 0x00000508
#define PRAMDAC_PLL_COEFF_SELECT 0x0000050C
+
+#define PEXTDEV_BASE 0x00101000
+
#define NV3_MIN_CLOCK_IN_KHZ 25000 // Not sure about this, but it seems reasonable
#define NV3_MAX_CLOCK_IN_KHZ 230000
#define NV4_MAX_CLOCK_IN_KHZ 350000
static int max_clock, is_nv3, pll_coeff;
-/* NTSC cards have approx 14.3Mhz. Need to detect, but leave for now*/
-#define PLL_INPUT_FREQ 13500
+static int PLL_INPUT_FREQ;
#define M_MIN 7
#define M_MAX 13
@@ -107,79 +196,102 @@
#define P_MAX 4 /* Not sure about this. Could be 4 */
//=== Function section ===
-// From xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/riva_hw.c in XFree86 3.3.6
+// From xc/programs/Xserver/hw/xfree86/drivers/nv/nv_hw.c in X11R6.7.0
/*
* Calculate the Video Clock parameters for the PLL.
*/
-static int CalcVClock
-(
+static void CalcVClock (
int clockIn,
- int double_scan,
int *clockOut,
- int *mOut,
- int *nOut,
- int *pOut/*,
- RIVA_HW_INST *chip*/
+ unsigned int *pllOut
)
{
- unsigned lowM, highM, highP;
+ unsigned lowM, highM;
unsigned DeltaNew, DeltaOld;
unsigned VClk, Freq;
unsigned M, N, P;
-
+
DeltaOld = 0xFFFFFFFF;
- VClk = (unsigned)clockIn;
- if (double_scan)
- VClk *= 2;
-
- if (/*chip->CrystalFreqKHz*/PLL_INPUT_FREQ == 14318)
- {
- lowM = 8;
- highM = 14 - (/*chip->Architecture == NV_ARCH_03*/is_nv3);
- }
- else
- {
+ VClk = (unsigned)clockIn;
+
+ if (/*pNv->CrystalFreqKHz*/ PLL_INPUT_FREQ == 13500) {
lowM = 7;
highM = 13 - (/*chip->Architecture == NV_ARCH_03*/is_nv3);
+ } else {
+ lowM = 8;
+ highM = 14 - (/*chip->Architecture == NV_ARCH_03*/is_nv3);
}
- highP = 4 - (/*chip->Architecture == NV_ARCH_03*/is_nv3);
- for (P = 0; P <= highP; P ++)
- {
+ for (P = 0; P <= 4 - is_nv3; P++) {
Freq = VClk << P;
- if ((Freq >= 128000) && (Freq <= /*chip->MaxVClockFreqKHz*/max_clock))
- {
- for (M = lowM; M <= highM; M++)
- {
- N = (VClk * M / /*chip->CrystalFreqKHz*/PLL_INPUT_FREQ) << P;
- Freq = (/*chip->CrystalFreqKHz*/PLL_INPUT_FREQ * N / M) >> P;
- if (Freq > VClk)
- DeltaNew = Freq - VClk;
- else
- DeltaNew = VClk - Freq;
- if (DeltaNew < DeltaOld)
- {
- *mOut = M;
- *nOut = N;
- *pOut = P;
- *clockOut = Freq;
- DeltaOld = DeltaNew;
+ if ((Freq >= 128000) && (Freq <= max_clock)) {
+ for (M = lowM; M <= highM; M++) {
+ N = ((VClk << P) * M) / /* pNv->CrystalFreqKHz */ PLL_INPUT_FREQ;
+ if(N <= 255) {
+ Freq = ((/*pNv->CrystalFreqKHz*/ PLL_INPUT_FREQ * N) / M) >> P;
+ if (Freq > VClk)
+ DeltaNew = Freq - VClk;
+ else
+ DeltaNew = VClk - Freq;
+ if (DeltaNew < DeltaOld) {
+ *pllOut = (P << 16) | (N << 8) | M;
+ *clockOut = Freq;
+ DeltaOld = DeltaNew;
+ }
}
}
}
}
- return (DeltaOld != 0xFFFFFFFF);
+}
+
+static void CalcVClock2Stage (
+ int clockIn,
+ int *clockOut,
+ unsigned int *pllOut,
+ unsigned int *pllBOut
+)
+{
+ unsigned DeltaNew, DeltaOld;
+ unsigned VClk, Freq;
+ unsigned M, N, P;
+
+ DeltaOld = 0xFFFFFFFF;
+
+ *pllBOut = 0x80000401; /* fixed at x4 for now */
+
+ VClk = (unsigned)clockIn;
+ for (P = 0; P <= 6; P++) {
+ Freq = VClk << P;
+ if ((Freq >= 400000) && (Freq <= 1000000)) {
+ for (M = 1; M <= 13; M++) {
+ N = ((VClk << P) * M) / (PLL_INPUT_FREQ << 2);
+ if((N >= 5) && (N <= 255)) {
+ Freq = (((PLL_INPUT_FREQ << 2) * N) / M) >> P;
+ if (Freq > VClk)
+ DeltaNew = Freq - VClk;
+ else
+ DeltaNew = VClk - Freq;
+ if (DeltaNew < DeltaOld) {
+ *pllOut = (P << 16) | (N << 8) | M;
+ *clockOut = Freq;
+ DeltaOld = DeltaNew;
+ }
+ }
+ }
+ }
+ }
}
// Set the clock to the given speed (in KHz)
Bool RIVA128ClockSelect( int clockspeed )
{
- int *ptr;
+ int *ptr, *ptr2;
+ int implementation = 0;
- int out;
- int m, n, p, value;
+ int clockout;
+ int pll, pllB;
int i = 0;
pciConfigPtr pcr = NULL;
int fd;
@@ -203,13 +315,101 @@
if (pcr->_device == PCI_DEVICE_ID_NVIDIA_TNT ||
pcr->_device == PCI_DEVICE_ID_NVIDIA_TNT2 ||
pcr->_device == PCI_DEVICE_ID_NVIDIA_UTNT2 ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_UNKNOWN_TNT2 ||
pcr->_device == PCI_DEVICE_ID_NVIDIA_VTNT2 ||
pcr->_device == PCI_DEVICE_ID_NVIDIA_UVTNT2 ||
- pcr->_device == PCI_DEVICE_ID_NVIDIA_ITNT2)
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_ITNT2 ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_QUADRO ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX400 ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX200 ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2 ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460 ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440 ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420 ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX440SE ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO32 ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_460GO ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_460_GO64 ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_QUADRO4_200 ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_410_GO16 ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX440_AGP8x ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX440SE_AGP8x ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX420_AGP8x ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_448_GO ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_488_GO ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_QUADRO4_580_XGL ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_QUADRO4_280_NVS ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_QUADRO4_380_XGL ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_IGEFORCE2 ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_IGEFORCE4_MX ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE3 ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE3_TI200 ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE3_TI500 ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_QUADRO_DCC ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI4600 ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI4400 ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI4200 ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI4800 ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI4200_AGP8x ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI4800SE ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_4200GO ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_QUADRO4_700GOGL ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_QUADRO4_980XGL ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_QUADRO4_780XGL ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5800U ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5800 ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_QUADRO_FX_2000 ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1000 ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600U ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600 ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600SE ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5600 ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5650 ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO700 ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200 ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200U ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200 ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200SE ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5200 ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5250 ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5200_32M_64M ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_QUADRO_NVS_280_PCI ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_QUADRO_FX_500 ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5300 ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5100 ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900U ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900 ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900XT ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5950U ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_QUADRO_FX_3000 ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700U ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700 ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700LE ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700VE ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700 ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700 ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO1000 ||
+ pcr->_device == PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1100)
{
is_nv3 = 0;
pll_coeff = 0x00010700;
max_clock = NV4_MAX_CLOCK_IN_KHZ;
+ implementation = pcr->_device & 0x0ff0;
break;
}
@@ -249,6 +449,33 @@
return FALSE;
}
+ ptr2 = (int*)mmap(0, 0x1000,PROT_READ|PROT_WRITE,MAP_SHARED, fd, (off_t)(pcr->_base0) + PEXTDEV_BASE);
+
+ if( ptr2 == (int*)-1 )
+ {
+ PERROR(( "Error mmap'ing /dev/mem" ));
+ return FALSE;
+ }
+
+ if(is_nv3)
+ {
+ PLL_INPUT_FREQ = (ptr2[0x00000000/4]&0x20) ? 13500 : 14318;
+ }
+ else
+ {
+ PLL_INPUT_FREQ = (ptr2[0x00000000/4]&0x40) ? 14318 : 13500;
+ }
+
+ if((implementation == 0x0170) ||
+ (implementation == 0x0180) ||
+ (implementation == 0x01F0) ||
+ (implementation >= 0x0250))
+ {
+ if(ptr2[0x00000000/4] & (1 << 22)) PLL_INPUT_FREQ = 27000;
+ }
+
+ munmap(ptr2, 0x1000);
+
close( fd );
#else
ptr=(int*) malloc(0x4000);
@@ -261,13 +488,15 @@
// Calculate the clock
//NV3ClockSelect( (float)clockspeed, &out, &m, &n, &p );
- CalcVClock ((float) clockspeed, 0, &out, &m, &n, &p);
-
- value = (m) + (n<<8) + (p<<16);
+ if ((implementation == 0x0310) || (implementation == 0x0340)) {
+ CalcVClock2Stage ((float) clockspeed, &clockout, &pll, &pllB);
+ } else {
+ CalcVClock ((float) clockspeed, &clockout, &pll);
+ }
// But of debug info
- PDEBUG(( "Wanted %dkHz, got %dkHz (m=%d, n=%d, p=%d, value=0x%08X)\n",
- clockspeed, (int)out, m, n, p, value ));
+ PDEBUG(( "Wanted %dkHz, got %dkHz (pll=0x%08X)\n",
+ clockspeed, (int)clockout, pll));
// Default value is 0x00000100 (NV3)
// X uses 0x10010100 (NV3) or 0x10000700 (NV4)
@@ -275,8 +504,10 @@
ptr[PRAMDAC_PLL_COEFF_SELECT/4] = pll_coeff; // could use |=
// Divide by 4 because we're dealing with integers
- ptr[PRAMDAC_PLL_COEFF/4] = value;
-
+ ptr[PRAMDAC_PLL_COEFF/4] = pll;
+ if ((implementation == 0x0310) || (implementation == 0x0340)) {
+ ptr[0x00000578/4] = pllB;
+ }
#ifndef DOS
// Unmap memory
munmap( ptr, 0x1000 );
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